Transcription
ADVANCED ASIC CHIP SYNTHESISUsing Synopsys Design Compiler"and PrimeTime
Trademark InformationUNIX is a registered trademark of UNIX Systems Laboratories, Inc.Veri log is a registered trademark of Cadence Design Systems, Inc.RSPF and DSPF is a trademark of Cadence Design Systems , Inc.SDF and SPEF is a trademark of Open Verilog International.Synopsys, PrimeTime, Formality, DesignPower, DesignWare and SOLV-IT! areregistered trademarks of Synopsys, Inc.Design Analyzer, Design Compiler, Test Compiler, VHDL Comp iler, HDLCompiler, ECO Compiler, Library Compiler, Synthetic Libraries, DesignTime,Floorplan Manager, characterize, dont touch, dont touch network and uniquify, aretrademarks of Synopsys, Inc.SolvNET is a service mark of Synopsys, Inc.All other brand or product names mentioned in this document, are trademarks orregistered trademarks of their respective companies or organizations.All ideas and concepts provided in this book are authors own, and are not endorsedby Synopsys, Inc. Synopsys, Inc. is not responsible for information provided in thisbook .
ADVANCED ASIC CHIP SYNTHESISUsing Synopsys Design Compiier and PrimeTime Himanshu BhathagarConexant Systems, Inc.(Formerly, Rockwell Semiconductor Systems).,.Springer Science Business Media, LLC
Library of Congress Cataloging-in-Publication DataBhatnagar, Himanshu.Advanced ASIC chip synthesis : Using Synopsys Design Compiler andPrimeTime / Himanshu Bhatnagar.p. cm.ISBN 978-1-4613-4662-3ISBN 978-1-4419-8668-9 (eBook)DOI 10.1007/978-1-4419-8668-91. Application specific integrated circuits--Design and construction--Dataprocessing. 2. Logic design--Data processing. 3. Computer-aided design. 4.Compilers (Computer programs)1. Title.TK7874.6.B44 1999621.39'5--dc2199-24720CIPCopyright 1999 by Springer Science Business Media New YorkOriginally published by Kluwer Academic Publishers in 1999Softcover reprint of the hardcover 18t edition 1999AlI rights reserved. No part of this publication may be reproduced, stored ina retrieval system or transmitted in any form or by any means, mechanical,photo-copying, recording, or otherwise, without the prior written permission ofthe publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park,Norwell, Massachusetts 02061Printed on acid-free paper.
To my wife Nivedita,and my daughter Nayana
About The AuthorxxvCHAPTER 1: ASIC DESIGN METHODOLOGY11.1Typical Design Flow1.1.1Specification and RTL Coding1.1.2Dynamic Simulation1.1.3Constraints, Synthesis and Scan Insertion1.1.4Formal Verification1.1.5Static Timing Analysis using PrimeTime1.1.6Placement, Routing and Verification1.1 .7Engineering Change Order1.2Chapter Summary2567910111314
CHAPTER2: 2.5.22.6161718182326283035363942Example DesignInitial SetupPre-Layout StepsSynthesisStatic Timing Analysis using PrimeTimeSDF GenerationVerificationFloorplanning and RoutingPost-Layout StepsStatic Timing Analysis using PrimeTimePost-Layout OptimizationChapter SummaryCHAPTER 3: BASIC 6062Synopsys ProductsSynthesis EnvironmentStartup FilesSystem Library VariablesObjects, Variables and AttributesDesign ObjectsVariablesAttributesFinding Design ObjectsSynopsys FormatsData OrganizationDesign EntryCompiler DirectivesHDL Compiler DirectivesVHDL Compiler DirectivesChapter SummaryCHAPTER 4: SYNOPSYS TECHNOLOGY LIBRARY63Library Basics4.1Library Group4.1.1Library Level Attributes4.1.2646464
ContentsEnvironment Description4.1.3Cell Description4.1.44.2Delay Calculation4.2.1Delay Model4.2.2Delay Calculation ProblemsWhat is a Good Library?4.3Chapter Summary4.465CHAPTER 5: PARTITIONING AND CODING 6Partitioning for SynthesisWhat is RTL?Software versus HardwareGeneral GuidelinesTechnology IndependenceClock LogicNo Glue Logic at the TopModule Name Same as File NamePads Separate from Core LogicMinimize Unnecessary HierarchyRegister All OutputsGuidelines for FSM SynthesisLogic InferenceIncomplete Sensitivity ListsMemory Element InferenceMultiplexer InferenceThree-State InferenceOrder DependencyBlocking versus Non-Blocking Assignments in VerilogSignals versus Variables in VHDLChapter SummaryCHAPTER 6: CONSTRAINING DESIGNS6.1Environment and Constraints6.1.1Design Environment6.1.2Design Constraints6.2Advanced Constraints6.3Clocking 959696979899100100105110113
6.3.1Pre-Layout6.3.2Post-Layout6.3.3Generated Clocks6.4 Putting it Together6.5 Chapter Summary114115116117119CHAPTER 7: OPTIMIZING 1142145145Design Space ExplorationTotal Negat ive SlackCompilation StrategiesTop-Down Hierarchical CompileTime -Budgeting Resolving Multiple InstancesOptimization TechniquesCompiling the DesignFlatten ing and StructuringRemoving HierarchyOptim izing Clock NetworksOptimizing for AreaChapter SummaryCHAPTER 8: DESIGN FOR TEST1478.1Types ofDFTMemoryBIST8.1.18.1.2Boundary Scan DFT8.2Scan InsertionMaking Design Scannable8.2.18.2.2Test Pattern Generation8.3 DFT GuidelinesTri-State Bus Contention8.3.18.3.2LatchesGated Reset or Preset8.3.3Gated or Generated Clocks8.3.4Use Single Edge ofthe Clock8.3.5Multiple Clock Domains8.3.6Order Scan-Chains to Minimize Clock S
ContentsLogic Un-Scannable due to Memory Element8.3.88.4Chapter Summary156158CHAPTER 9: LINKS TO LAYOUT & POST-LAYOUT 186187189193194Generating Netlist for LayoutUniquifyTailoring the Netlist for LayoutRemove Unconnected PortsVisible Port NamesVerilog Specific StatementsUnintentional Clock or Reset GatingUnresolved ReferencesLayoutFloorp1anningClock Tree InsertionTransfer of Clock Tree to Design CompilerRoutingExtractionPost-Layout OptimizationBack Annotation and Custom Wire LoadsIn-Place OptimizationLocation Based OptimizationFixing Hold-Time ViolationsFuture DirectionsChapter SummaryCHAPTER 10: SDF GENERATION195SDF File10.1SDF File Generation10.210.2.1Generating Pre-Layout SDF FileGenerating Post-Layout SDF File10.2.2Issues Related to Timing Checks10.2.310.2.4False Delay Calculation ProblemPutting it Together10.2.5Chapter Summary10.3196198198201202203205207
CHAPTER 11: PRIMETIME uctionInvoking PTPrimeTime EnvironmentAutomatic Command ConversionTel BasicsCommand SubstitutionListsFlow Control and LoopsPrimeTime CommandsDesign EntryClock SpecificationTiming Analysis CommandsOther Miscellaneous CommandsChapter Summary211212213213215215215216221227230CHAPTER 12: STATIC TIMING 244245247248249249254254256Why Static Timing Analysis?What to Analyze?Timing ExceptionsMulticyele PathsFalse PathsDisabling Timing ArcsDisabling Timing Arcs IndividuallyCase AnalysisEnvironment and ConstraintsOperating Conditions - A DilemmaPre-LayoutPre-Layout Clock SpecificationTiming AnalysisPost-LayoutWhat to Back Annotate?Post-Layout Clock SpecificationTiming AnalysisAnalyzing ReportsPre-Layout Setup-Time Analy sis ReportPre-Layout Hold-Time Analysis Report
Contents12.7.3Post-Layout Setup-Time Analysis Report12.7.4Post-Layout Hold-Time Analysis Report12.8Advanced Analysis12.8.1Detailed Timing Report12.8.2Cell Swapping12.8.3Bottleneck Analysis12.8.4Clock Gating Checks12.9Chapter Summary258260262262265266269272APPENDIX275INDEX277
ForewordOur semiconductor industry is increasingly characterized by acceleratedproduct obsolescence . As a result, business success is increasingly dependentupon the ability of development teams to deliver a shortest "time-to-market"product that meets customer requirements . Early product introduction meanshigher profit margins, lasting only until slower-to-market competitors enterand erode prices.This intense cycle of market price erosion has been particularly evident in thepersonal computer industry over the last few years. Consumers arecontinually demanding quality products at lower cost but with increasingfeatures. Semiconductor suppliers are, in tum, driven to develop system-ona-chip (SoC) products utilizing VDSM (Very-Deep-Sub-Micron)technologies, just to remain competitive.Several high performance tools and techniques have been developed over thepast few years to mitigate somewhat this "time-to-market" pressure and toenable rapid design updates to meet evolving customer specifications. Thesechanges have resulted in a redefinition of standard ASIC design flowmethodologies. High level design languages, like VHDL and Verilog, havedisplaced schematic capture, thus promoting design reuse. Dynamicsimulation has given way to formal verification and static timing analysis. In
addition, synthesis engines have become more sophisticated, targetingcomplex designs containing millions of gates and large IP cores. It is nowestimated that the number of gates in a complex ASIC will approach 10million early in the next decade.Successfully achieving these levels of integration in a time-to-market focuseddevelopment environment will require an intimate knowledge of ASICdesign flow in the VDSM realm and a complex integration of productsoffered by multiple EDA tool vendors.This book, written by Himanshu Bhatnagar, provides a comprehensiveoverview of the ASIC design flow targeted for VDSM technologies using theSynopsys suite of tools. It emphasizes the practical issues faced by thesemiconductor design engineer in terms of synthesis and the integration offront-end and back-end tools. Traditional design methodologies arechallenged and unique solutions are offered to help define the nextgeneration of ASIC design flows. The author provides numerous practicalexamples derived from real-world situations that will prove valuable topracticing ASIC design engineers as well as to students of advanced VLSIcourses in ASIC design.Dr. Dwight W. DeckerChairman and CEO, Conexant Systems, Inc.(Formerly, Rockwell Semiconductor Systems)Newport Beach, California, U.S.A.
PrefaceThis book describes the advanced concepts and techniques used towardsASIC chip synthesis, formal verification and static timing analysis, using theSynopsys suite of tools. In addition, the entire ASIC design flowmethodology targeted for VDSM (Very-Deep-Sub-Micron) technologies iscovered in detail.The emphasis ofthis book is on real-time application of Synopsys tools, usedto combat various problems seen at VDSM geometries. Readers will beexposed to an effective design methodology for handling complex, submicron ASIC designs. Significance is placed on HDL coding styles,synthesis and optimization, dynamic simulation, formal verification, DFTscan insertion, links to layout, and static timing analysis. At each step,problems related to each phase of the design flow are identified, withsolutions and work-arounds described in detail. In addition, crucial issuesrelated to layout, which includes clock tree synthesis and back-endintegration (links to layout) are also discussed at length. Furthermore, thebook contains in-depth discussions on the basics of Synopsys technologylibraries and HDL coding styles, targeted towards optimal synthesis solution.Target audiences for this book are practicing ASIC design engineers andgraduate level students undertaking advanced VLSI courses on ASIC chipdesign and DFT techniques.
This book is not intended as a substitute or a replacement for the Synopsysreference manual, but is meant for anyone who is involved in the ASICdesign flow. Also, it is useful for those designers (and companies) who donot have layout capability, or their own technology libraries, but rely onoutside vendors for back-end integration and final fabrication of the device.The book provides alternatives to traditional method of netlist hand-off tooutside vendors because of various issues related to VDSM technologies. Italso addresses solutions to common problems faced by designers wheninterfacing various tools from different EDA tool vendors.Overview of the ChaptersChapter 1 presents an overview to various stages involved in the ASICdesign flow using Synopsys tools. The entire design flow is briefly described,starting from concept to chip tape-out. This chapter is useful for designerswho have not delved in the full process of chip design and integration, butwould like to learn the full process of ASIC design flow.Chapter 2, outlines the practical aspects of the ASIC design flow as describedin Chapter 1. Beginners may use this chapter as a tutorial. Advanced users ofSynopsys tools may benefit by using this chapter as a reference. Users withno prior experience in synthesis using Synopsys tools should skip thischapter and return to it later after reading the remaining book.The basic concepts related to synthesis are described in detail in Chapter 3.These concepts introduce the reader to synthesis terminology usedthroughout the later chapters. Readers will find the information provided hereuseful by gaining a basic understanding of these tools and their environment.In addition to describing the purpose of each tool and their setup, this chapteralso focuses on defming objects, variables, attributes and compiler directivesused by the Design Compiler.Chapter 4 describes the basics of the Synopsys technology library. Designersusually do not concern themselves with the full details of the technologylibrary, as long as the library contains a variety of cells with different drivestrengths. However, a rich library usually determines the quality of synthesis.Therefore, the intent of this chapter is to describe the Synopsys technologylibrary from the designer's perspective. Focus is provided on delay
calculation method and other techniques that designers may use in order toalter the behavior of the technology library, hence the quality of thesynthesized design.Proper partitioning and good coding style is essential in obtaining qualityresults. Chapter 5 provides guidelines to various techniques that may be usedto correctly partition the design in order to achieve the optimal solution. Inaddition, the HDL coding styles is covered in this chapter that illustratesnumerous examples and provides recommendations to designers on how tocode the design in order to produce faster logic and minimum area.The Design Compiler commands used for synthesis and optimization aredescribed in Chapter 6. This chapter contains information that is useful forthe novice and the advanced users of Synopsys tools. The chapter focuses onreal-world applications by taking into account deviations from the idealsituation i.e., "Not all designs or designers, follow Synopsysrecommendations" . The chapter illustrates numerous examples that helpguide the user in real-time application of the commands.Chapter 7 discusses optimization techniques in order to meet timing and arearequirements. Comparison between older version of Design Compiler and thenew version is highlighted. Emphasis is provided on the new optimizationtechnique employed by Design Compiler called "TNS". Also, detailedanalysis on various methods used for optimizing logic is presented. Inaddition, different compilation strategies, each with advantages anddisadvantages are discussed in detail.DFT techniques are increasingly gaining momentum among ASIC designengineers. Chapter 8 provides a brief overview of the different types of DFTtechniques that are in use today, followed by detailed description on howdevices can be made scannable using Synopsys's Test Compiler. It describescommands used for inserting scan through Design Compiler. A multitude ofguidelines is presented in order to alleviate the problems related to DFT scaninsertion on a design.Chapter 9 discusses the links to layout feature of Design Compiler. Itdescribes the interface between the front-end and back-end tools. Also, thischapter provides different strategies used for post-layout optimization of
designs. This includes in-place and location based optimization techniques.Furthermore, a section is devoted to clock tree insertion and issues related toclock tree transfer to Design Compiler. Various solutions to this commonproblem are described . This chapter is extremely valuable for designers (andcompanies) who do not posses their own layout tool, but would like to learnthe place and route process along with full chip integration techniques.Chapter 10, titled "SDF Generation: for Dynamic Timing Simulation"describes the process of generating the SDF file from Design Compiler orPrimeTime . A section is devoted to the syntax of SDF format, followed bydetailed discussion on the process of SDF generation, both for pre and postlayout phases of the design. In addition, few innovative ideas and suggestionsare provided to facilitate designers in performing successful simulation. Thischapter is useful for those designers who prefer dynamic simulation methodto formal verification techniques, in order to verify the functionality of thedesign.Chapter 11 introduces to the reader, the basics of static timing analysis, usingPrimeTime . This includes a brief section devoted to Tel language that isutilized by PrimeTime. Also described in this chapter are selected PrimeTimecommands that are used to perform static timing analysis, and also facilitatethe designer in debugging the design for possible timing violations.The key to working silicon usually lies in successful completion of statictiming analysis performed on a particular design. This capability makes statictiming analysis one of the most important steps in the entire design flow andis used by many designers as a sign-off criterion to the ASIC vendor. Chapter12 is devoted to several basic and advanced topics on static timing analysis,using PrimeTime. It effectively illustrates the usage of PrimeTime, both forthe pre and the post-layout phases of the ASIC design flow process. Inaddition, numerous examples on analyzing reports and suggestions onvarious scenarios are provided. This chapter is useful to those who wouldlike to migrate from traditional methods of dynamic simulation to the methodof analyzing designs statically. It is also helpful for those readers who wouldlike to perform in-depth analysis of the design through PrimeTime.
Conventions Used in the BookAll Synopsys commands are typed in "Arie l" font. This includes all examplesthat contain synthesis and timing analysis scripts.The command line prompt is typed in "Cou r i e r New" font. For example:de shell and,Option values for some of the commands are enclosed in and . In general,these values need to be replaced before the command can be used. Forexample:set falseyath -from from list -to to list The "\" character is used to denote line continuation, whereas thecharacter represents the "OR" function. For example:"I"compile -map effort low I medium I high \-lncrernentaljnapplnqWherever possible, keywords are italicized. Topics or points, that needemphasis are underlined or highlighted through bold font.
AcknowledgementsI would like to express my heartfelt gratitude to a number of people whocontributed their time and effort towards this book. Without their help, itwould have been impossible to take this enormous undertaking.First and foremost, a special thanks to my family, who gave me continuoussupport and encouragement that kept me constantly motivated towards thecompletion of this project. My wife Nivedita, who patiently withstood mynocturnal and weekend writing activities, spent enormous amount of timetowards proofreading the manuscript and correcting my "Engineers English".I could not have accomplished this task without her help and understanding.I would like to thank my supervisor, Anil Mankar for giving me amplelatitude at work, to write the book. His moral support and innovativesuggestions kept me alert and hopeful. I would also like to thank mycolleagues at Conexant; Hoat Nguyen, Dao Doan, ChiIan Nguyen, RandyKolar, Chung Jue Chen, Chih-Shun Ding, Steve Schulz, Khosrow Golshan,Richard Ward, Sameer Rao and Ravi Ranjan who devoted their precious timein reviewing the manuscript.I was extremely fortunate to have an outstanding reviewer for this project,Dr. Kelvin F. Poole (Clemson University, S.C.). I have known Dr. Poole fora number of years and approached him for his guidance while writing thisbook. He not only proofread the entire manuscript word-by-word (gritting his
teeth, I'm sure!), but also provided valuable suggestions, which helped makethe book more robust. Thank you Dr. Poole.I wish to express my thanks to Bill Mullen, Ahsan Bootehsaz, Steve Meier,Russ Segal, Juergen Froessl and Amanda Hsiao at Synopsys, whoparticipated in reviewing this manuscript and provided me with manyvaluable suggestions. Julie Liedtke and Bryn Ekroot of Synopsys helped mewrite the necessary Trademark information. Special thanks are also due toKameshwar Rao, Jeff Echtenkamp, Heratch Avakian, and Chin-Sieh Lee ofBroadcom Corporation for providing me valuable feedback and engaging inlengthy technical discussions. Thanks are also due to Jean-Claude Marin(SGS-Thomson Microelectronics, France), Tapan Mohanti (FairchildSemiconductors), Dr. Sudhir Aggarwal (Philips Semiconductors), AbuHoraira (Intel Corporation), Phong Tran (Chameleon Technologies), KarimHussain, Kevin Walis and Ginsy Chagger (Factor Technologies, U.K.) forgiving me positive feedback at all times. Their endless encouragement isvery much appreciated.When I first started this project, I contacted Carl Harris of Kluwer AcademicPublishers and described to him this idea. He immediately got excited andgave me the go-ahead. Although I taxed his patience many times, he still keptme on my toes and pushed me towards completing this book. Hisunderstanding even when I kept on delaying the book is appreciated.A final word, "Thank you Mom and Dad for all the sacrifices you made tofurther my career".Himanshu BhatnagarConexant Systems, Inc.Newport Beach, California
About The AuthorHimanshu Bhatnagar is a Senior ASIC Design Engineer at ConexantSystems, Inc. based in Newport Beach, California. Conexant Systems Inc.,formerly Rockwell Semiconductor Systems, is the world's largestindependent company focused exclusively on providing semiconductorproducts for communication electronics. Himanshu has been instrumental indefining the next generation ASIC design flow methodologies using latesthigh performance tools from Synopsys and other EDA tool vendors.Before Joining Conexant, Himanshu worked for SGS-ThomsonMicroelectronics in Singapore and the corporate headquarters based inGrenoble, France. He completed his undergraduate degree in Electronics andComputer Science from Swansea University (Wales, U.K), and his mastersdegree in VLSI design from Clemson University, (South Carolina, USA).
3.1 Synopsys Products 43 3.2 Synthesis Environment 45 3.2.1 Startup Files 45 3.2.2 System Library Variables 47 3.3 Objects, Variables and Attributes 48 3.3.1 Design Objects 48 3.3.2 Variables 49 3.3.3 Attributes 51 3.4 Finding Design Objects 52 3.5 Synopsys Formats 53 3.6 Data Organization 54 3.7 Design Entry 55 3.8 CompilerDirectives 56 3.8.1 .
