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Technical ArticleMS-2374differential voltage level is reduced to make physicalimplementation easier by reducing required slew rates inthe drivers.To allow for more flexibility, the JESD204B revision transitionsfrom the frame clock to the device clock. Previously, in theJESD204 and JESD204A revisions, the frame clock was theabsolute timing reference in the JESD204 system. Typically,the frame clock and the sampling clock of the converter(s)were usually the same. This did not offer a lot of flexibilityand could cause undesired complexity in system designwhen attempting to route this same signal to multipledevices and account for any skew between the differentrouting paths. In JESD204B, the device clock is the timingreference for each element in the JESD204 system. Eachconverter and receiver receives their respective device clockfrom a clock generator circuit which is responsible forgenerating all device clocks from a common source. Thisallows for more flexibility in the system design but requiresthat the relationship between the frame clock and deviceclock be specified for a given device.Figure 4. CMOS, LVDS, and CML Driver Power ComparisonAt approximately 150 MSPS to 200 MSPS and 14 bits ofresolution, CML output drivers start to become moreefficient in terms of power consumption. CML offers theadvantage of requiring less number of output pairs per agiven resolution than LVDS and CMOS drivers due to theserialization of the data. The CML drivers specified for theJESD204B interface have an additional advantage since thespecification calls for reduced peak-to-peak voltage levels asthe sample rate increases and pushes up the output line rate.The number of pins required for the same give converterresolution and sample rate is also considerably less. Table 1gives an illustration of the pin counts for the three differentinterfaces using a 200 MSPS converter with various channelcounts and bit resolutions. The data assumes a synchronizationclock for each channel’s data in the case of the CMOS andLVDS outputs and a maximum data rate of 4.0 Gbps forJESD204B data transfer using the CML outputs. The reasonsfor the progression to JESD204B using CML drivers becomeobvious when looking at this table and observing the dramaticreduction in pin count that can be achieved.JESD204—WHY SHOULD WE PAY ATTENTIONTO IT?In much the same way as LVDS began overtaking CMOS asthe technology of choice for the converter digital interfaceseveral years ago, JESD204 is poised to tread a similar pathin the next few years. While CMOS technology is still hangingaround today, it has mostly been overtaken by LVDS. Thespeed and resolution of converters as well as the desire forlower power eventually renders CMOS and LVDS inadequatefor converters. As the data rate increases on the CMOSoutputs, the transient currents also increase and result inhigher power consumption. While the current, and thus,power consumption, remains relatively flat for LVDS, theinterface has an upper speed bound that it can support.This is due to the driver architecture, as well as the numerousdata lines that must all be synchronized to a data clock.Figure 4 illustrates the different power consumptionrequirements of CMOS, LVDS, and CML outputs for a dual14-bit ADC.Page 3 of 4JESD204B Survival Guide 4

MS-2374Technical ArticleTable 1. Pin Count Comparison—200 MSPS ADCNumber of 1616CMOS Pin Count132652104153060120173468136LVDS Pin Count (DDR)142856112163264128183672144Analog Devices, Inc., market leader in data converters, hasseen the trend that is pushing the converter digital interfacetowards the JESD204 interface defined by JEDEC. AnalogDevices has been involved with the standard from thebeginning when the first JESD204 specification was released.To date, Analog Devices has released to production severalconverters with the JESD204 and JESD204A compatibleoutputs and is currently developing products with outputsthat are compatible with JESD204B. The AD9639 is a quadchannel 12-bit 170 MSPS/210 MSPS ADC that has a JESD204interface. The AD9644 and AD9641 are 14-bit 80 MSPS/155 MSPS dual and single ADCs that have the JESD204Ainterface. From the DAC perspective, the recently releasedAD9128 is a dual 16-bit 1.25 GSPS DAC that has a JESD204Ainterface. For more information on Analog Devices efforts inregards to JESD204, please visit www.analog.com/jesd204.meet new requirements brought on by changes in convertertechnology. As system designs become more complex andconverter performance pushes higher, the JESD204 standardshould be able to adapt and evolve to continue to meet thenew design requirements necessary.As the speed and resolution of converters have increased, thedemand for a more efficient digital interface has increased.The industry began realizing this with the JESD204serialized data interface. The interface specification hascontinued to evolve to offer a better and faster way totransmit data between converters and FPGAs (or ASICs).The interface has undergone two revisions to improve uponits implementation and meet the increasing demandsbrought on by higher speeds and higher resolutionconverters. Looking to the future of converter digitalinterfaces, it is clear that JESD204 is poised to become theindustry choice for the digital interface to converters. Eachrevision has answered the demands for improvements on itsimplementation and has allowed the standard to evolve toShare this article onREFERENCESJEDEC Standard JESD204 (April 2006). JEDEC Solid StateTechnology Association. www.jedec.org.JEDEC Standard JESD204A (April 2008). JEDEC Solid StateTechnology Association. www.jedec.org.JEDEC Standard JESD204B (July 2011). JEDEC Solid StateTechnology Association. www.jedec.org.RESOURCESABOUT THE AUTHORJonathan Harris is a product applications engineer inthe High Speed Converter Group at Analog Devices(Greensboro, NC). He has over seven years of experience asan applications engineer, supporting products in the RFindustry. Jonathan received his MSEE from AuburnUniversity and his BSEE from UNC-Charlotte. He can bereached via email at jonathan.harris@analog.com.One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 www.analog.comTrademarks and registered trademarks are the property of theirrespective owners.TA11322-0-10/13(A)www.analog.com 2013 Analog Devices, Inc. All rights reserved.Page 4 of 45CML Pin Count (JESD204B)248162481624816 JESD204B Survival Guide

Technical ArticleMS-2304.High Speed ConverterSurvival Guide: Digital DataOutputsimpedance is usually less than a few hundred ohms. Thevoltage levels for CMOS swing from approximately VDD toground and can, therefore, be quite large depending on themagnitude of VDD.by Jonathan Harris, Product Applications Engineer,Analog Devices, Inc.IDEA IN BRIEFWith a multitude of analog-to-digital converters (ADCs)available for designers to choose from, an importantparameter to consider in the selection process is the typeof digital data outputs included. Currently, the three mostcommon types of digital outputs utilized by high speedconverters are complementary metal oxide semiconductor(CMOS), low voltage differential signaling (LVDS), andcurrent mode logic (CML). Each of these digital output typesused in ADCs has its advantages and disadvantages thatdesigners should consider in their particular application.These factors depend on the sampling rate and resolutionof the ADC, the output data rates, the power requirementsof the system design, and others. In this article, the electricalspecifications of each type of output will be discussed alongwith what makes each type suited for its particular application.These different types of outputs will be compared in terms ofphysical implementation, efficiency, and the applicationsbest suited for each type.a) Inverted Outputb) Noninverted OutputFigure 1. Typical CMOS Digital Output DriverSince the input impedance is high and the output impedanceis relatively low, an advantage that CMOS has is that oneoutput can typically drive multiple CMOS inputs. Anotheradvantage to CMOS is the low static current. The only instancewhere there is significant current flow is during a switchingevent on the CMOS driver. When the driver is in either alow state, pulled to ground, or in a high state, pulled to VDD,there is little current flow through the driver. However, whenthe driver is switching from a low state to a high state or from ahigh state to a low state, there is a momentary low resistancepath from VDD to ground. This transient current is one of themain reasons why other technologies are used for outputdrivers when converter speeds go beyond 200 MSPS.Another reason to note is that a CMOS driver is required foreach bit of the converter. If a converter has 14 bits, there are14 CMOS output drivers required to transmit each of thosebits. Commonly, more than one converter is placed in a givenpackage, and up to eight converters in a single package arecommon. When using CMOS technology, this could meanthat there would be up to 112 output pins required just forthe data outputs. Not only would this be inhibitive from apackaging standpoint, but it would also have high powerconsumption and increase the complexity of board layout.To combat these issues, an interface using low voltagedifferential signaling (LVDS) was introduced.CMOS DIGITAL OUTPUT DRIVERSIn ADCs with sample rates of less than 200 MSPS, it is commonto find that the digital outputs are CMOS. A typical CMOSdriver employed consists of two transistors, one NMOS andone PMOS, connected between the power supply (VDD) andground, as shown in Figure 1a. This structure results in aninversion in the output, so as an alternative, the back-toback structure in Figure 1b can be used in order to avoidthe inversion in the output. The input of the CMOS outputdriver is high impedance while the output is low impedance.At the input to the driver, the impedance of the gates of thetwo CMOS transistors is quite high since the gate is isolatedfrom any conducting material by the gate oxide. The impedances at the input can range from kilo ohms to mega ohms.At the output of the driver, the impedance is governed by thedrain current, ID, which is typically small. In this case, theLVDS DIGITAL OUTPUT DRIVERSLVDS offers some nice advantages over CMOS technology. Itoperates with a low voltage signal, approximately 350 mV,and is differential rather than single ended. The lower voltageswing has a faster switching time and reduces EMI concerns.By virtue of being differential, there is also the benefit ofPage 1 of 4www.analog.com 2013 Analog Devices, Inc. All rights reserved.JESD204B Survival Guide 6

MS-2304Technical Article(DDR) mode where two data bits can be routed through thesame LVDS output driver. This reduces the number of pinsrequired by one half compared to CMOS. In addition, theamount of power consumed for the same number of dataoutputs is reduced. LVDS does offer numerous benefits overCMOS for the data outputs of converters, but it eventuallyhas its limitations as CMOS does. As converter resolutionincreases, the number of data outputs required by an LVDSinterface becomes more difficult to manage for PCB layouts.In addition, the sample rates of converters eventually pushthe required data rates of the interface beyond the capabilitiesof LVDS.common-mode rejection. This means that noise coupledto the signals tends to be common to both signal paths andis mostly cancelled out by the differential receiver. Theimpedances in LVDS need to be more tightly controlled. InLVDS, the load resistance needs to be approximately 100 Ωand is usually achieved by a parallel termination resistor atthe LVDS receiver. In addition, the LVDS signals need to berouted using controlled impedance transmission lines. Thesingle-ended impedance required is 50 Ω while the differentialimpedance is maintained at 100 Ω. Figure 2 shows the typicalLVDS output driver.CML OUTPUT DRIVERSThe latest trend in digital output interfaces for convertersis to use a serialized interface that uses current mode logic(CML) output drivers. Typically, converters with higherresolutions ( 14 bits), higher speeds ( 200 MSPS), andthe desire for smaller packages with less power utilize thesetypes of drivers. The CML output driver is employed inJESD204 interfaces that are being used on the latest converters.Utilizing CML drivers with serialized JESD204 interfacesallows data rates on the converter outputs to go up to 12 Gbps(with the current revision of the specification JESD204B). Inaddition, the number of output pins required is dramaticallyreduced. Routing a separate clock signal is no longer necessarysince the clock becomes embedded in the 8b/10b encodeddata stream. The number of data output pins is also reducedwith a minimum of two being required. As the resolution,speed, and channel count of the converter increase, the numberof data output pins may be scaled to account for the greateramount of throughput required. Since the interface employedwith CML drivers is typically serial, however, the increasein the number of pins required is much smaller than thatcompared with CMOS or LVDS (the data transmitted in CMOSor LVDS is parallel, which requires a much great numberof pins).Figure 2. Typical LVDS Output DriverAs can be seen by the topology of the LVDS output driverin Figure 2, the circuit operation results in a fixed dc loadcurrent on the output supplies. This avoids current spikesthat would be seen in a typical CMOS output driver whenthe output logic state transitions. The nominal currentsource/sink in the circuit is set to 3.5 mA which results ina typical output voltage swing of 350 mV with a 100 Ωtermination resistor. The common-mode level of the circuitis typically set to 1.2 V, which is compatible with 3.3 V, 2.5 V,and 1.8 V supply voltages.There are two standards that have been written to define theLVDS interface. The most commonly used is the ANSI/TIA/EIA-644 specification entitled “Electrical Characteristics ofLow Voltage Differential Signaling (LVDS) Interface Circuits.”The other is the IEEE standard 1596.3 entitled “IEEEStandard for Low Voltage Differential Signals (LVDS) forScalable Coherent Interface (SCI).”Since CML drivers are employed in serialized data interfaces,the number of pins required is much smaller. Figure 3 showsa typical CML driver used for converters with JESD204 orsimilar data outputs. The figure gives a generalization of thetypical architecture of a CML driver. It shows the optionalsource termination resistor and the common-mode voltage.The inputs to the circuit drive the switches to the currentsources which drive the appropriate logic value to the twooutput terminals.LVDS does require that special attention be paid tothe physical layout of the routing of the signals but offersmany advantages for converters when sampling at speedsof 200 MSPS or greater. The constant current of the LVDSdriver allows for many outputs to be driven without thelarge amount of current draw that CMOS would require. Inaddition, it is possible to operate LVDS in a double-data ratePage 2 of 47 JESD204B Survival Guide

Technical ArticleMS-2304In the case of CML in the JESD204 interface, attention mustalso be directed to the routing paths between the digitaloutputs. There are significantly less data outputs to manage,so this task does become easier but cannot be neglectedaltogether. In this case, there should be no concern withregards to timing skew between the data outputs and theclock output since the clock is embedded in the data.However, attention must be given to an adequate clockand data recovery (CDR) circuit in the receiver.In addition to the skew, the setup and hold times must alsobe given attention with CMOS and LVDS. The data outputsmust be driven to their appropriate logic state in sufficienttime before the edge transition of the clock and must bemaintained in that logic state for a sufficient time after theedge transition of the clock. This can be affected by the skewbetween the data outputs and the clock outputs, so it isimportant to maintain good timing relationships. LVDShas the advantage over CMOS due to the lower signal swingsand differential signaling. The LVDS output driver does nothave to drive such a large signal to many different outputsand does not draw a large amount of current from the powersupply when switching logic states, as the CMOS driverwould. This makes it less likely for there to be an issuedelivering a change in logic state. If there were many CMOSdrivers switching simultaneously, the power supply voltagecould get pulled down and introduce issues driving the rightlogic values to the receiver. The LVDS drivers would maintain aconstant level of current such that this particular issue wouldnot arise. In addition, the LVDS drivers are inherently moreimmune to common-mode noise due to its use of differentialsignaling. The CML drivers have similar benefits to LVDS.These drivers also have a constant level of current, but unlikeLVDS, fewer numbers are required due to the serialization ofthe data. In addition, the CML drivers also offer immunity tocommon-mode noise since they also use differential signaling.Figure 3. Typical CML Output DriverA CML driver is similar to the LVDS driver in that itoperates in a constant current mode. This also gives theCML driver an advantage in terms of power consumption.Operating in a constant current mode requires fewer outputpins, and the total power consumption is reduced. As withLVDS, a load termination is required, as well as controlledimpedance transmission lines having a single-endedimpedance of 50 Ω and a differential impedance of 100 Ω.The driver itself may also have terminations, as shown inFigure 3, to help with any signal reflections due to the sensitivitywith such high bandwidth signals. In converters employingthe JESD204 standard, there are different specifications forthe differential and common-mode voltage levels dependingupon the speed of operation. Operating at speeds up to6.375 Gbps, the differential voltage level is nominally 8

JESD204B Survival Guide Practical JESD204B Technical Information, Tips, and Advice from the World's Data Converter Market Share Leader* *Analog Devices has a 48.5% global data converter market share, which is more than the next eight competitors combined, according to the analyst firm Databeans in its 2011 Data Converters Report. www.analog.com