WIXLIB

CprE 288 – Introduction to Embedded SystemsInstructors:Dr. Phillip Joneshttp://class.ece.iastate.edu/cpre2881

Announcements HW 6: Due Sunday (10/03) Quiz 6: Tuesday (10/5) – First 10 minutes of class usingCanvas– Class lectures– HW 4 & 5 & 6 material– Notes: Once sheet of notes (1-side) Exam 1: Thursday 10/7http://class.ece.iastate.edu/cpre2882

Overview Announcements Interrupts– Tiva TM4C123GH6PM Datasheet ( 8 pages) Chapter 2.5 – 2.54 (focus on Interrupt type Exceptions)– Table 2.9 Chapter 3. 4 NVIC registers– Enable (ENx)– Priority (PRIx) GPIO Interrupt Control : 10.2.2– Textbook reading: Section 2.4 (pg. 34-37) Chapter 5.1, 5.3.2http://class.ece.iastate.edu/cpre2886

Microcontroller / System-on-Chip rruptsDevicesADCGPIOPCTL0NVICCFG DATA STATUSXYTimersCFG DATA STATUSGPIO 0Port X (8-bits)7654CFG DATA STATUSUARTOutsideWorld8

ISR (INTERRUPT SERVICE ROUTINES)http://class.ece.iastate.edu/cpre2889

Interrupts and Interrupt Service Routines (ISRs) Interrupt: A mechanism that allows hardware to inform the CPUthat an event has occurred. Example hardware events:– Button connected to an GPIO port pressed– Data arrives to the system. e.g. new byte on UART interface, newsample from analog to digital converter (ADC)– Timer expires or Timer becomes equal to a given value– CPU tries to execute an invalid assembly instruction Interrupt Service Routine (ISR): code to be executed to deal withthe hardware event that has occurred. Also referred to as anInterrupt handler.http://class.ece.iastate.edu/cpre28810

General Interrupt to ISR flow1.2.3.4.Hardware event causes an interrupt to occurInterrupt notifies the CPUCPU pauses the programCPU disables interrupts and saves its “state”–The CPU state is the information the CPU needs to un-pausethe program properly. e.g. location of the instruction whenthe paused occurred, current CPU register values5. CPU re-enables interrupts and executes the proper ISR6. Once the ISR completes, the CPU disables interrupts andrestores its state to what it was before the interrupt occurred7. CPU re-enables interrupts, and continues the program fromwhere it paused.http://class.ece.iastate.edu/cpre28811

Nested Vector Interrupt Controller (NVIC) NVIC: the name of the hardware on the CPRE 288 microcontrollerchip that manages interrupts– Notifies CPU when an interrupt occurs– Programmer configures to enable/disable specific interrupts– Programmer configures to give interrupts priorities– Provides the CPU with information for accessing an InterruptVector Table, which stores the starting address (i.e. entry point)of each ISR. Interrupt Vector Table: Each row in this table (located in memory)contains the address of the starting instruction for each ISR. TheCPU uses this information to start execution of the ISR that hasbeen “triggered” by a corresponding Interrupt (i.e. 812

Interrupt Service Routine (ISR) Setup1. Enable the interrupt: (every interrupt has an enable bit): Use the datasheetto find the register name and bit position you need to set. Find the interrupt number on page 104 of the datasheet and set a 1to its bit in the NVIC ENn R register. Where n is 0-4 and indicates agroup of 32 interrupts (i.e. 0 - 0-31, 1- 32-63, etc). The bit you setis the (interrupt number - (32*n))th bit.2. Bind the handler (i.e. indicate where to go when an interrupt event occurs) Find the corresponding Interrupt vector number for your interrupt.(datasheet, page 104). Alternatively the timer interrupt vectors aredefined as INT TIMERxn where x is 0-5 and n is A or B. Call IntRegister(interrupt vector number, handler name) to bind theinterrupt(s) to your handler (i.e. ISR name). IntRegister can be foundin interrupt.h3. Write the ISR (Interrupt Service Routine) The ISR is a function, or block of code, the CPU will call for youwhenever the interrupt event occurs. You define/program what typeof processing should occur for a given type of interrupt event.http://class.ece.iastate.edu/cpre28813

15

Microcontroller / System-on-Chip rruptsDevicesADCGPIOPCTL0NVICCFG DATA STATUSXYTimersCFG DATA STATUSGPIO 0Port X (8-bits)7654CFG DATA STATUSUARTOutsideWorld17

Generic Interrupt UISRInterrupt ControllerGlobal Interrupt.Control Reg Local Interrupt Control Reg. Local Interrupt Flag Reg. http://class.ece.iastate.edu/cpre28818

NVIC – GPIO ExampleNVICNVIC ENx R GPIO PORTx MIS R GPIO PORTx IM R GPIO PORTx RIS R Local Devicehttp://class.ece.iastate.edu/cpre28819

NVIC – GPIO ExampleNVICNVIC ENx R Bit-wise ORGPIO PORTx MIS R GPIO PORTx IM RGPIO PORTx RIS RBit-wise OR GPIO PORTx IEV R GPIO PORTx IBE state.edu/cpre288LowLevel GPIO PORTx IS R21

NVIC – GPIO ExampleBit-wise OR GPIO PORTx MIS R GPIO PORTx IM RBit-wise ORGPIO PORTx RIS RWhichinputtriggers aninterrupt? GPIO PORTx IEV R GPIO PORTx IBE RRisingEdgeHighLevelFallingEdgeLowLevel GPIO PORTx IS Rhttp://class.ece.iastate.edu/cpre28823

GPIO PORTx IS R: Interrupt Sense Reg1 level-sensitive interrupts0 edge-sensitive interrupts(pg. 664)24

GPIO PORTx IBE R: Interrupt Both Edges Reg.0 Interrupt generation via GPIO PORTx IEV register1 Both edges trigger interrupt(pg. 665)25

GPIO PORTx IEV R: Interrupt Event Reg.0 Interrupt generation via Low level or falling edge1 Interrupt generation via High level or rising edge(pg. 666)26

GPIO PORTx IM R: Interrupt Mask Reg.0 Interrupt is masked1 Interrupt can be sent to interrupt controller(pg. 667)27

GPIO PORTx RIS R: Raw Interrupt Status Reg.0 An interrupt has not occurred1 An interrupt has occurred(pg. 668)28

GPIO PORTx MIS R: Masked Interrupt Status Reg.0 Interrupt is masked or has not occurred1 An interrupt has occurred and was sent to theinterrupt controller(pg. 669)29

GPIO PORTx ICR R: Interrupt Clear Reg.0 Interrupt is unaffected1 An interrupt has been cleared(pg. 670)30

NVIC Enx R: NVIC Enable Reg.Four register groups (EN0 EN3) which indicatewhether an interrupt is enabled or disabled in the NVIC Table 2-9 (pg 104) has interrupt assignments31

IntRegister(INT GPIOx, gpiox handler)Function that binds interrupts between “GPIOx” and thehandler function “gpiox handler”32

CprE 288 – Introduction to Embedded Systems