Transcription
Fundamentals of Computer SystemsSequential LogicStephen A. EdwardsColumbia UniversitySummer 2016
State-Holding ElementsBistable ElementsRS LatchD LatchPositive-Edge-Triggered D Flip-FlopD Flip-Flop with EnableSynchronous Digital LogicThe Synchronous ParadigmShift RegistersCountersTiming in Synchronous CircuitsFlip-Flop TimingTiming in Synchronous CircuitsClock Skew
State-Holding Elements
Bistable ElementsQQQQEquivalent circuits; right is more traditional.Two stable states:0110
A Bistable in the WildThis “debounces” the coin switch.Breakout, Atari 1976.
RS LatchRSQR QSRS00110101QQQQ
RS LatchR01SQR QS10RSQQSetRS00110101QQ10QQSet
RS LatchR01SQR QS00QRSQQRSQQ00110101Q1Q0QHold, State 1HoldSet
RS LatchR10SQR QS01QRSQQRSQQ00110101Q10Q01QResetHoldSetReset
RS LatchR00SQR QS01QRSQQRSQQ00110101Q10Q01QHold, State 0HoldSetReset
RS LatchR10SQR QS10QRSQQRSQQ00110101Q100Q010QHuh?HoldSetResetBad
RS LatchR01SQR QS10QRSQQRSQQ00110101Q100Q010QSetHoldSetResetBad
RS LatchR01SQR QS00RSQQ00110101Q100Q010QQRSQQHold, State 1HoldSetResetBad
RS LatchR10SQR QS10RSQQ00110101Q100Q010QQRSQQHuh?HoldSetResetBad
RS LatchR0XSQR tBad
SR Latches in the WildGenerates horizontal and vertical synchronizationwaveforms from counter bits.Stunt Cycle, Atari 1976.
D LatchDQD QCC QQinputsoutputsCDQQ011X01Q01Q10
A ChallengeA simple traffic light controller.Want the lights to cycle green-yellow-red.D QCRD QCYD QCGDoes this work?
Positive-Edge-Triggered D Flip-FlopMasterD1CMCCDCMtransparentD0CSQopaqueD QCD00CSSlaveD QCQD Q
Positive-Edge-Triggered D Flip-FlopMasterD1CMCCDCMtransparentD0CSQopaqueD QCD00CSSlaveD QCQD Q
Positive-Edge-Triggered D Flip-FlopMasterD0CMD tSlaveD QCQD Q
Positive-Edge-Triggered D Flip-FlopMasterD0CMD tSlaveD QCQD Q
Positive-Edge-Triggered D Flip-FlopMasterD1CMD QCD00SlaveD paqueD0CSQopaqueD Q
Positive-Edge-Triggered D Flip-FlopMasterD0CMD QCD01SlaveD QCQD entopaquetransparentD0CSQopaque
The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.D QRD QYD QGCLKCLKRYG
The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.D QRD QYD QGCLKCLKRYG
The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.D QRD QYD QGCLKCLKRYG
The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.D QRD QYD QGCLKCLKRYG
The Traffic Light Controller: A second tryLet’s try this again with D flip-flops.D QRD QYD QGCLKCLKRYG
The Traffic Light Controller with ResetRESETCLKCLKRESETRYGD QRD QYD QG
The Traffic Light Controller with ResetRESETCLKCLKRESETRYGD QRD QYD QG
The Traffic Light Controller with ResetRESETCLKCLKRESETRYGD QRD QYD QG
The Traffic Light Controller with ResetRESETCLKCLKRESETRYGD QRD QYD QG
The Traffic Light Controller with ResetRESETCLKCLKRESETRYGD QRD QYD QG
The Traffic Light Controller with ResetRESETCLKCLKRESETRYGD QRD QYD QG
D Flip-Flop with Enable01DD QQECDD QCEDQ 011XXX01XXQ01QQ01QECWhat’s wrong with thissolution?
Asynchronous Preset/ClearPRED QCLRCLKDPRECLRQ
The Traffic Light Controller w/ Async. ResetRESETPRED QRCLKCLRPRED QYCLRPRED QCLRG
The Synchronous Digital Logic ParadigmGates and Dflip-flops onlyEach flip-flopdriven by thesame clockEvery cyclicpath containsat least oneflip-flopOUTPUTSINPUTSSTATECLOCKNEXT STATECL
Cool Sequential Circuits: Shift RegistersQ0ACLKQ1Q2Q3AQ0 Q1 Q2 10
Universal Shift 1S0Operation00110101Shift rightLoadHoldShift left
Cool Sequential Circuits: CountersCycle through sequences of numbers, e.g.,00011011
The 74LS163 Synchronous Binary Counter
Flip-Flop TimingSetup Time: Time beforethe clock edge after whichthe data may not changetsuCLKDQ
Flip-Flop TimingSetup Time: Time beforethe clock edge after whichthe data may not changetsuCLKDQthHold Time: Time after theclock edge after which thedata may change
Flip-Flop TimingSetup Time: Time beforethe clock edge after whichthe data may not changetsuthCLKDQMinimum PropagationDelay: Time from clockedge to when Q mightstart changingtp(min)Hold Time: Time after theclock edge after which thedata may change
Flip-Flop TimingSetup Time: Time beforethe clock edge after whichthe data may not changetsuHold Time: Time after theclock edge after which thedata may changethCLKDQMinimum PropagationDelay: Time from clockedge to when Q mightstart changingtp(min)tp(max)Maximum PropagationDelay: Time from clockedge to when Qguaranteed stable
Timing in Synchronous Circuits···QCLD···CLKtcCLKQDtc : Clock period. E.g., 10 ns for a 100 MHz clock
Timing in Synchronous Circuits···QCLD···CLKSufficient Hold Time?tp(min,FF)tp(min,CL)CLKQDHold time constraint: how soon after the clock edge can Dstart changing? Min. FF delay min. logic delay
Timing in Synchronous Circuits···QCLD···CLKtp(max,FF)Sufficient Setup Time?tp(max,CL)CLKQDSetup time constraint: when before the clock edge is Dguaranteed stable? Max. FF delay max. logic delay
Clock Skew: What Really Happens···QCLK1CLDCLK2···CLKSufficient Hold Time?tskewCLK1CLK2QDtp(min,FF)tp(min,CL)CLK2 arrives late: clock skew reduces hold time
Clock Skew: What Really Happens···QCLK1CLDCLK2···CLKSufficient Setup Time?tskewCLK1CLK2QDtp(max,FF)tp(max,CL)CLK2 arrives early: clock skew reduces setup time
The Traffic Light Controller with Reset D Q D Q D Q CLK RESET R Y G CLK RESET R Y G. The Traffic Light Controller with Reset D Q D Q D Q CLK RESET R Y G CLK RESET R Y G. D Flip-Flop with Enable D Q Q 0 D 1 C E C E D Q " 0 X Q " 1 0 0 " 1 1 1 0 X X Q 1 X X Q D Q E C D Q What’s wrong with this solution? A
