Transcription
VHDL TutorialBy:Shahed ShahirEmail: sshahir@engmail.uwaterloo.ca
Outline VHDL Quick erate if StatementSelected Signal AssignmentGenericsHow to develop VHDL code using Xilinx ProjectNavigator
VHDL Quick LookEntityArchitectureAll the available signal types and functions can be imported by adding :Library ieee;In C:#include stdio.h
Entityentity entity identifier isPort( signal identifier : mode type ; signal identifier : mode type ; signal identifier : mode type );end entity identifier ;modetypeInStd acterSTD logicW(Week Unknown)U(Uninitialized)Example:X(Unknown)entity QuarterAdder isport(i a : in std logic;i b : in std logic;o s : out std logic);end QuarterAdder ;- (Don’t Care)L (Week Low)H (Weak High)Z (High impedance)
Architecturearchitecture architecture name of entity identifier is[ architecture declarative part]begin architecture statement ; architecture statement ; architecture statement ;Concurrent statementsend architecture name ;Example:architecture main of QuarterAdder isbegino s i a xor i b;end main;Int main (void){Printf(“Hello World”);}
ComponentComponent entity identifier Port( signal identifier : mode type ; signal identifier : mode type ; signal identifier : mode type );end Component;
VHDL Code For HalfAdderentity HalfAdder isport(i a : in std logic;i b : in std logic;o s : out std logic;o c : out std logic);end HalfAdder ;architecture main of HalfAdder iscomponent QuarterAdderport(i a : in std logic;i b : in std logic;o s : out std logic);end component;begino c i a and i b;QuarterAdder portend main;map( i a, i b, o s);
FullAddLibrary iieee;Use ieeeEntity FullAdd isport (i a, i b,i c : in std logic;o s,o c : out std logic);End FullAdd;Architecture main of FullAdd isBegingo s i c xor i a xor i b;o c (i c and ( i a or i b)) or (i a and i b);End main;
Generate-If StatementLibrary ieee;Use ieeeEntity adder isPort ("# downto%"# downtoo c: out std logic);End adder;Architecture main of adder isComponent fulladdPort(i a, i b, i c : in std logic;o s,o c : out std logic);End component;Component halfaddPort(i a,i b :in std logic;o s,o c : out std logic);End component;!& !& ! '"# "# downtodownto: “): “”;”;Signal initialization
Generate-If Statement (con’t)Begindownto #!# #* #!# #*halfadd--Label, - . 'End generate;) * #!# #(%fulladd, - . 'End generate;) * / ! / #!# #Fulladdi : fulladdPort map(a(i), b(i), carry(i 'End generate;End generate;( !)a i a;o s s;End main;Generate with ifConcurrent statements
Selected Signal AssignmentWith expression select target waveform when choice ; waveform when choice ; waveform when others;Example:Library ieee;0 # ###Entity muxone is, !!"# downtoo q:out std logic);End muxone;Architecture main of muxone isBeginWith i c select12 #!“ ”;#!“ ”;#!“ ”;#! # End main;
Generics345657 # 6&!port(clk,r: IN std logic;64"# width - );1805"# width - ));#! #9:; 653;50:3 !*# * # 6&.* #!12 others ‘ ’); End infer!
LIBRARY IEEE;port(clk,r: IN std logic;downto !"# downto !""%&'('&)* % %generic(width:positive;reset value : positive);port(clk,r: IN std logic;d:IN std logic vector(width- downto !"q:OUT std logic vector(width- downto !");end component;begin,generic map (reset value -.(clk/ / /# "%/ width -. " *,
How To Develop VHDL CodeUsing Xilinx Project Navigator
This brief tutorial will help you on how to start a VHDLproject on Xilinx , # 4" #. ' #.
new projectSelect a Name for the projectSelect Schematic as the project typeClick Next
Select the device propertiesClick Next
Click on New SourceSelect a name for your VHDL codeChoose VHDL moduleClick Next and click nextClick finish
Click nextClick nextClick finish
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VHDL Quick Look Entity Architecture All the available signal types and functions can be imported
