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Connectivity SolutionsConnectivity SolutionsHigh-Speed Serial I/O Made Simple – A Designers’ Guide, with FPGA ApplicationsHigh-Speed Serial I/0 Made SimpleA Designers‘ Guide, with FPGA ApplicationsHow Do You Get 10-Gbps I/O Performance?High-speed serial I/O can be used to solve system interconnect design challenges.Such I/Os, when integrated into a highly programmable digital environmentsuch as an FPGA, allow you to create high-performance designs that were neverpossible before. This book discusses the many aspects of high-speed serial designswith real world examples of how to implement working designs, including: Basic I/O Concepts – Differential signaling, SystemSynchronous, and Source Synchronous design techniques. Pros and Cons of different implemenations – How to evaluate thecost advantages, the reduced EMI, the maximum data flow, and so on. SERDES Design – Basic theory, how to implement highly efficientserial to parallel channels, coding schemes, and so on. Design Considerations – Standard and custom protocols, signalintegrity, impedance, shielding, and so on. Testing – Interpreting eye patterns, reducing jitter, interoperabilityconsiderations, bit error testers, and so on.Edition 1.0Xcell Publications help you solve design challenges, bringingyou the awareness of the latest tools, devices, and technologies;knowledge on how to design most effectively; and the nextsteps for implementing working solutions. See all of our books,magazines, technical journals, solutions guides, and brochuresat: www.xilinx.com/xcellEdition 1.0April, 2005PN 0402399Edition 1.0High-Speed Serial I/OMade SimpleA Designers’ Guide, with FPGA Applicationsby Abhijit Athavaleand Carl ChristensenR
CONNECTIVITY SOLUTIONS: EDITION 1.0High-Speed Serial I/OMade SimpleA Designer’s Guide with FPGA ApplicationsbyAbhijit AthavaleMarketing Manager, Connectivity Solutions, Xilinx, Inc.andCarl ChristensenTechnical MarketingPRELIMINARY INFORMATION
HIGH-SPEED SERIAL I/O MADE SIMPLE 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included hereinare trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of theirrespective owners.NOTICE OF DISCLAIMER: The information stated in this book is “Preliminary Information” and is not to beused for design purposes. Xilinx is providing this design, code, or information "as is." By providing thedesign, code, or information as one possible implementation of this feature, application, or standard, Xilinxmakes no representation that this implementation is free from any claims of infringement. You areresponsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaimsany warranty whatsoever with respect to the adequacy of the implementation, including but not limited toany warranties or representations that this implementation is free from claims of infringement and anyimplied warranties of merchantability or fitness for a particular purpose.All terms mentioned in this book are known to be trademarks or service marks and are the property of theirrespective owners. Use of a term in this book should not be regarded as affecting the validity of any trademark orservice mark.All rights reserved. No part of this book may be reproduced, in any form or by any means, without written permission from the publisher.For copies of this book, write to:Xilinx Connectivity SolutionsProduct Solutions Marketing/Xilinx Worldwide MarketingDept. 2450, 2100 Logic Drive, San Jose, CA 95124Tel: 408.879.6889, Fax: 308.371.8283serialio@xilinx.comPreliminary Edition 1.0April 2005PN0402399 ii
AcknowledgementsWe would like to offer our deepest thanks to Paul Galloway and Craig Abramson. Without their constantmotivation, direction, and encouragement, we could not have completed this project.We are also indebted to Ryan Carlson for his invaluable assistance in structuring the book, and to ChuckBerry for his great support and sales interface.To a host of reviewers that included Matt DiPaolo, Mike Degerstrom, and Scott Davidson, we want to offerour gratitude. They kept us honest, accurate, and up to date.To Babak Hedayati and Tim Erjavec for their unwavering support and encouragementFinally, we offer special thanks to Ray Johnson. He fully supported our effort and placed his personal stampof approval on this book by providing the Forward.PRELIMINARY INFORMATION iii
HIGH-SPEED SERIAL I/O MADE SIMPLE iv
TABLE OF CONTENTSAcknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iiiForewordAbout the Authors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiIntroductionI/O Performance Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Digital Design Solutions for I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Introducing Multi-Gigabit Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1History of Digital Electronic Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Basic I/O Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Differential Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4System-Synchronous, Source-Synchronous, and Self-Synchronous . . . . . . . . . . . . . .5Parallel Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Constant I/O Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Why Do We Need Gigabit Serial I/O?Design Concerns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Gigabit Serial I/O Advantages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Maximum Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Pin Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Simultaneous Switching Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Predefined Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16What are the Disadvantages?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Where Will Gigabit I/O Be Used? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Chip-to-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Board-to-Board/Backplanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Box-to-Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18The Future of Multi-gigabit Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18TechnologyReal-World Serial I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Gigabit-Serial Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20History of SERDES and CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20Basic Theory of Operations and Generic Block Diagram . . . . . . . . . . . . . . . . . . .21Why Are They So Fast? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Line Encoding Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25PRELIMINARY INFORMATIONXilinx v
HIGH-SPEED SERIAL I/O MADE SIMPLE 8b/10b Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Running Disparity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Control Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Comma Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4b/5b 64b/66b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4b/5b 64b/66b Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Introduction to Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Reference Clocking Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Clock Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Receive and Transmit Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Channel Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Physical Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Differential Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Line Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Optical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Realities of Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .FEC Used in Some Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .SERDES Technology Facilitates I/O Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ning with Gigabit Serial I/OThe Challenges of Multi-Gigabit Transceiver Design. . . . . . . . . . . . . . . . . . . . . . . . . . .Design Considerations and Choices You Can Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Standard Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Custom Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Shielding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Boards, Connectors, and Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Printed Circuit Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Connector Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Cable Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vi Xilinx57575758626565667373737981838384
TABLE OF CONTENTSTest and Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86Sampling Oscilloscopes and Digital Communication Analyzers . . . . . . . . . . . . . .86Time Delay Reflectometer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87Eye Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93Generators and Bit Error Testers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94Putting the Equipment to Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96Multi-gigabit Debug Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous, and Source Synchronous design techniques. Pros and Cons of different implemenations– How to evaluate the cost advantages, the reduced EMI, the maximum data flow, and so on. SERDES Design– Basic theory, how to implement highly efficient serial to parallel channels, coding schemes, and so on. Design Considerations– Standard and custom protocols, signal integrity, impedance .
