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AN3203Application noteEVL250W-ATX80PL: 250W ATX SMPSdemonstration boardIntroductionThis application note describes the characteristics and performance of a 250 W wide rangeinput and power factor corrected power supply designed to be used in an ATX application.Good electrical performance allows meeting the most demanding efficiency targets.The converter consists of four main blocks: A PFC front-end stage using the L6563S PFC controller which generates the 400 V busvoltage. An AHB (Asymmetrical half bridge) stage using the L6591 ZVS half bridge controllerwhich performs the conversion from the high voltage bus to the 12 V output providinginsulation. Two DC-DC post-regulator stages using the L6727 which obtain the 5 V and 3.3 Voutputs from the 12 V bus. An auxiliary power supply (STANDBY) stage using the VIPer27H in isolated flybackconfiguration which provides the 5 V SB output with 10 W power capability.Figure 1.January 2011250 W ATX SMPS demonstration boardDoc ID 17402 Rev 21/49www.st.com
ContentsAN3203Contents1Main characteristics and circuit description . . . . . . . . . . . . . . . . . . . . . 52Asymmetrical half bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 12342.1AHB typical waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Complete system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.1Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.2Load transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173.3Standby operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1Efficiency measurement and no-load consumption . . . . . . . . . . . . . . . . . 194.2Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.3Harmonic content measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.4Single output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275Conducted noise measurements (pre-compliance test) . . . . . . . . . . . 306Parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327PFC coil specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407.189Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40AHB transformer specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418.1Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418.2Mechanical aspect and pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 42AUX flyback transformer specification . . . . . . . . . . . . . . . . . . . . . . . . . 449.1Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449.2Mechanical aspect and pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 4610PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4711Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482/49Doc ID 17402 Rev 2
AN3203List of tablesList of tablesTable 1.Table 2.Table 3.Table 4.Table 5.Table 6.Table 7.Table 8.Table 9.Table 10.Table 11.Table 12.Table 13.Table 14.Table 15.Table 16.Table 17.Efficiency @ 115 Vrms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Efficiency @ 230 Vrms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1980 PLUS program efficiency levels (115Vac). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1980 PLUS program efficiency levels (230 Vac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Climate Savers Computing Initiative (for multi-output PSU) . . . . . . . . . . . . . . . . . . . . . . . . 20No-load consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Low load efficiency @ 115 Vrms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Low load efficiency @ 230 Vrms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22PF vs. load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Single output efficiency @ 115 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Single output efficiency @ 230 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27AHB efficiency with 400 Vdc input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29EVL250W-ATX80PL bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Winding characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Winding characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Winding characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Doc ID 17402 Rev 23/49
List of figuresAN3203List of figuresFigure 1.Figure 2.Figure 3.Figure 4.Figure 5.Figure 6.Figure 7.Figure 8.Figure 9.Figure 10.Figure 11.Figure 12.Figure 13.Figure 14.Figure 15.Figure 16.Figure 17.Figure 18.Figure 19.Figure 20.Figure 21.Figure 22.Figure 23.Figure 24.Figure 25.Figure 26.Figure 27.Figure 28.Figure 29.Figure 30.Figure 31.Figure 32.Figure 33.Figure 34.Figure 35.Figure 36.Figure 37.Figure 38.Figure 39.4/49250 W ATX SMPS demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Electrical diagram: input EMI filter and PFC stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Electrical diagram: AHB stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Electrical diagram: DC-DC stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Electrical diagram: standby stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11AHB primary side key waveforms @ full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12AHB zero voltage switching detail @ full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13AHB transitions detail @ 20 % rated load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14AHB secondary side key waveforms @ full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Short-circuit behavior detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Load transient on 12 V output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Load transient on 5 V output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Load transient on 3.3 V output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Efficiency vs. O/P power @ 115 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Efficiency vs. O/P power @ 230 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21No-load consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Efficiency at low loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Fanless board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24EN61000-3-2 and JEITA-MITI measurements @ full load . . . . . . . . . . . . . . . . . . . . . . . . . 25EN61000-3-2 and JEITA-MITI measurements @ 75 W in . . . . . . . . . . . . . . . . . . . . . . . . . 25PF vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26THD vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Single output efficiency @ 115 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Single output efficiency @ 230 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28AHB stage only efficiency (Vin 400 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29CE peak measurement@115 Vac and full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30CE peak measurement @ 230 Vac and full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30CE average measurement@115 Vac and full load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31CE average measurement@230 Vac and full load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Mechanical drawing (unit: mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Windings position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Windings position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Top side silk screen and copper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Bottom side silk screen and copper (mirror view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Doc ID 17402 Rev 2
AN32031Main characteristics and circuit descriptionMain characteristics and circuit descriptionHere are the main characteristics of the power supply: Input mains range:–Vin: 88 264 Vrms–f: 45 66 HzOutputs:– 12 Vdc 2 % - 13.5 A– 5 Vdc 2 % - 12 A– 3.3 Vdc 2 % - 8 A– 5 V SB 2 % - 2 A Standby consumption: 0.2 W Protection: –Short-circuit–Overload–Output overvoltage–BrownoutPCB type and size:–FR4–Double side CU 70 µm–148 x 120 mm Safety: according to EN60950 EMI: according to EN55022 - class BThe EVL250W-ATX80PL demonstration board is made up of four main blocks, theschematics are shown in Figure 2, 3, 4, and 5.The front-end PFC stage is realized using a boost topology working in line modulated fixedoff time (LM-FOT) mode, described in STMicroelectronics’ application notes, AN1792;Design of Fixed-Off-Time controlled PFC pre-regulators with the L6562 and AN3142;Solution for designing a 400 W Fixed-Off-Time controlled PFC preregulator with the L6563Sand L6563H. The LM-FOT operation offers the advantage of having CCM operation (withlower rms current with respect to TM mode) without the need to use a complex andexpensive controller. Therefore, it is possible to use the simple L6563S, enhanced TM PFCcontroller, which integrates all the functions and protection, needed to control the stage, andan interface with the downstream DC-DC converter.The power stage of the PFC is realized with inductor L4, MOSFET Q1 and Q2, diode D3,and capacitor C1. The LM-FOT operation is obtained with components D6, R15, C10, R14,C9, R13, and Q3.The PFC delivers a stable high voltage bus ( 400 V nominal) to the downstream converters(AHB and flyback) and provides for the reduction of the current harmonics drawn from themains, in order to meet the requirements of the European EN61000-3-2 norm and theJapanese JEITA-MITI norm.The second stage is an asymmetrical half bridge converter, driven by the L6591, aSTMicroelectronics controller dedicated to this topology. This IC integrates all the functionsDoc ID 17402 Rev 25/49
Main characteristics and circuit descriptionAN3203and protection needed by the AHB stage and an interface for the PFC controller. The L6591includes two gate drivers for the half bridge MOSFETs and a fixed frequencycomplementary PWM logic with 50 % maximum duty cycle with programmable dead timeand current mode control technique.Other features of this IC are pulse-by-pulse overcurrent protection, transformer saturationdetection, overload protection (latched or auto-restart), and programmable soft-start. Thereis also a high voltage startup circuit, a burst mode logic for low load operation, and theadaptive UVLO onboard, which are not used in this design as they are designed for adapterapplications (see AN2852).The following is a description of the power circuit of this stage. The half bridge switchesQ101 and Q102 are connected to the output voltage of the PFC. The half bridge node drivesthe series of C101 (DC blocking capacitor) and the primary side of the transformer T1. Thistransformer has two secondary windings with a center tap connected to the secondaryground. The other ends are connected to the sources of MOSFETs Q201 and Q202, whichreplace output diodes in order to perform the synchronous rectification. Two extra windingsallow, with few external passive components, a self driven synchronous rectification to beobtained. This solution allows efficiency to be increased without the extra cost of adedicated SR controller IC.Q201 and Q202 drains are connected to the output inductor L201 that, together with outputcapacitors C201 and C202, acts as a low pass filter. The signal 12 VA is then post filtered(with L5 and C207) to obtain the 12 V output voltage.The design of transformer T1 is a trade-off between ZVS operation and the requiredelectrical performance/efficiency. ZVS can be obtained acting on the magnetizinginductance or on the primary side leakage inductance. In more detail, ZVS could be met by: Decreasing the magnetizing inductance Increasing the leakage inductanceLow values of magnetizing inductance generate high magnetizing current. This helps toreach ZVS but it also increases the total primary side rms current and therefore the relatedlosses. In this design a value of 500 µH has been selected.On the other hand, ZVS could be obtained by increasing the leakage inductance. If such aparameter is increased, the primary side current takes more time before reversing itsdirection and therefore ZVS is more easily met. A high leakage inductance value leads toduty cycle losses, reducing the effective range of duty cycle usable. This creates problemswith hold-up requirements and makes it necessary to work with very narrow duty cycles withnominal input voltage generating high rms currents in the circuit.A value of 12 µH has been selected as the leakage inductance.Because of these reasons, in this design ZVS is always met at low side MOSFET turn-onwhile it is met only for medium-high loads at high side MOSFET turn-on. Even at mediumlow loads Q101 is turned on with a Vds well below the half bridge input voltage.The L6591 LINE pin is used for startup sequencing. It shares with the L6563S the voltagedivider made up of R20, R21, R22, R29, and R26 that senses the PFC output voltage. TheAHB stage is activated when the bulk voltage reaches about 380 V.The DISABLE pin (latched protection) is driven by the L6563S PWM LATCH pin and stopsthe AHB stage in case of PFC feedback disconnection.The oscillator is programmed in order to have a switching frequency of about 80 KHz and touse the minimum dead time (about 310 ns).6/49Doc ID 17402 Rev 2
AN3203Main characteristics and circuit descriptionThe PFC STOP pin is the interface for the PFC controller, it is connected to the L6563SRUN pin through R104 and it stops the PFC operation (not latched) in case of overload,output short-circuit or transformer saturation detection.The 5 V and 3.3 V are obtained from the 12 VA bus (AHB output) thanks to two DC-DCconverters mounted on two daughter boards. These stages are driven by the L6727, singlephase PWM controller. The topology is a standard step down. For more information pleaserefer to the L6727; Single phase PWM controller datasheet.The last stage is the auxiliary power supply that provides the 5 V SB output (2A capability)and the VCC supply for the L6563S and L6591. It is realized with a standard flybacktopology operating in CCM/DCM with fixed frequency using the VIPer27H. This stage takesthe PFC output voltage as input and is always working when the mains is plugged in. TheVIPer27H has all the protection needed to safely drive the standby stage. It protects thecircuitry in case of overload, output short-circuit, or output overvoltage.All the other stages (and therefore the outputs 12 V, 5 V and 3.3 V) can be turned on /off using the signal PS ON. If it is disconnected or connected to GND, the OPTO2 current iszero, Q601 is open and the VCC of the L6563S and L6591 is zero. If PS ON is connected to 5 V SB, the OPTO2 current turns Q601 on. This BJT, together with the Zener diodeZD601, acts as a linear regulator and provides the supply to the PFC and AHB controllers.The same optocoupler is used to turn off the PFC and AHB stages in case of an overvoltageon one of the three main outputs. Such protection is realized with three Zener diodes (onefor each output) that set the OVP thresholds. If one of the three output voltages goes over itsthreshold, the Zener diode conducts and turns on the latch realized with Q604 and Q605.The current in OPTO2 is reduced to zero (overriding the PS ON information) and theL6563S and L6591 are turned off.Only the 5 V SB stays on and continues to keep the protection latched.Doc ID 17402 Rev 27/49
Main characteristics and circuit descriptionFigure 2.8/49Electrical diagram: input EMI filter and PFC stageDoc ID 17402 Rev 2AN3203
AN3203Figure 3.Main characteristics and circuit descriptionElectrical diagram: AHB stage!- V Doc ID 17402 Rev 29/49
Main characteristics and circuit descriptionFigure 4.AN3203Electrical diagram: DC-DC stage!- V 10/49Doc ID 17402 Rev 2
AN3203Figure 5.Main characteristics and circuit descriptionElectrical diagram: standby stage!- V Doc ID 17402 Rev 211/49
Asymmetrical half bridge operationAN32032Asymmetrical half bridge operation2.1AHB typical waveformsIn Figure 6 the primary side key waveforms during steady-state operation with full loadapplied are shown. Figure 7 shows the detail of the two transitions during one switchingcycle.The AHB stage has been designed to operate at about 80 kHz with a nominal input voltageof 400 V (PFC output bus). The transformer design is the result of a trade-off between thehalf bridge MOSFETs zero voltage switching (ZVS) operation requirements, the primary rmscurrent, and duty cycle losses. In fact, ZVS can be achieved by reducing the magnetizinginductance or increasing the leakage inductance. With the output power of this board, thefirst solution implies having very high rms primary current which leads to high losses. Thesecond solution introduces the so called “duty cycle losses”. When the leakage inductanceis de-magnetizing, the voltages on the secondary side windings are zero and therefore theoutput mean value is reduced with respect to the same half bridge duty cycle and negligibleleakage inductance. Duty cycle losses limit the hold-up capability of the power supplybecause they increase the minimum input voltage that guarantees output regulation.In this design the system works with ZVS for both MOSFETs at full load. Because of theintrinsic asymmetry of the topology the behavior of the two switches is different. When theload is reduced the low side MOSFET always operates in ZVS while the high side one startsloosing ZVS. The high side MOSFET never turns on with full bus voltage applied between itsdrain and source. As shown in Figure 8, even at 20 % of rated load the Vds at turn-on isabout 100 V, definitely lower compared with the 400 V of a hard switching solution.This design can therefore meet both efficiency and dynamic requirements.Figure 6.AHB primary side key waveforms @ full loadCh1: LVG pin voltage (yellow)Ch3: HVG pin voltage (purple)Ch4: Primary winding current (green)12/49Doc ID 17402 Rev 2
AN3203Asymmetrical half bridge operationThe signal HVG is the sum of the half bridge node (FGND pin of L6591) and the high sidegate driver voltages. This peculiarity allows both waveforms and the ZVS operation for thehigh side MOSFET to be checked. The driver activation is visible on the HVG signal whenthere is a small voltage step on the high part of the waveform.Figure 7.AHB zero voltage switching detail @ full loadCh1: LVG pin voltage (yellow)Ch3: HVG pin voltage (purple)Ch4: Primary winding current (green)Doc ID 17402 Rev 213/49
Asymmetrical half bridge operationFigure 8.AN3203AHB transitions detail @ 20 % rated loadCh1: LVG pin voltage (yellow)Ch3: HVG pin voltage (purple)Ch4: Primary winding current (green)The key waveforms at the secondary side are shown in Figure 9. It is interesting to note that,while the current is swapped between the two SR MOSFETs, the voltage at their drain isnearly zero. The time required for current swap is directly proportional to the primaryleakage inductance. As mentioned before, the effect of this phenomenon is the duty cyclelosses.14/49Doc ID 17402 Rev 2
AN3203Asymmetrical half bridge operationFigure 9.AHB secondary side key waveforms @ full loadCh2: Q201 and Q202 drain pin (blue)Ch3: FGND pin voltage (purple)Ch4: Diode D13 current (green)In order to improve the overall efficiency of the power supply, synchronous rectification hasbeen used. The two AHB output diodes have been replaced with two MOSFETs. A selfdriven technique has been used to obtain a cheap solution. Two extra windings at thesecondary side generate the two square waves that, opportunely shifted, drive the two SRMOSFETs gates directly. Referring to Q201, the extra winding (realized with just one turn)starts from transformer pin 10 and ends in TON DR FLYWIRE. C210, D204, and R216 areused to shift the voltage at the correct level to drive the MOSFET. R202 helps to keep theMOSFET off if no driving signal is applied. A similar circuit drives the gate of Q202 startingfrom the TOFF DR FLYWIRE signal.Doc ID 17402 Rev 215/49
Asymmetrical half bridge operation2.2AN3203Short-circuit protectionIn case of a short-circuit at the AHB output the overload protection (OLP) is activated.Figure 10 shows the pins involved in this function. When the short-circuit is applied, theCOMP pin saturates high. The IC detects this condition and starts charging the SScapacitor. When the SS voltage reaches 5 V the system is shut down, when it reaches 6.4 Vthe IC is latched. The PFC controller is also stopped: when the L6591 activates theprotection, the PFC STOP signal pulls the L6563S RUN pin down to below the 0.8Vthreshold. The latch is kept thanks to the auxiliary stage that remains active and providesthe VCC voltage.In order to restart the system it is necessary to recycle the L6591 VCC voltage between theUVLO thresholds. This can be done by removing the PS ON signal in the auxiliary stage.Figure 10. Short-circuit behavior detailCh1: SS pin voltage (yellow)Ch2: COMP pin voltage (blue)Ch3: FGND pin voltage, (purple)Ch4: L6563S RUN pin voltage (green)16/49Doc ID 17402 Rev 2
AN3203Complete system3Complete system3.1Overvoltage protectionEvery output is protected against overvoltage. The 12 V, 5 V and 3.3 V are monitored onthe auxiliary power supply schematic page. They use three Zener diodes to fix the threeovervoltage thresholds. In case one of the three voltages exceeds its threshold the latchrealized with Q604 and Q605 is turned on and the VCC for the L6591 and L6563S isremoved.The two outputs 5 V and 3.3 V also have an overvoltage protection integrated into theL6727 controller.The 5 V SB output is protected using the OVP protection of the VIPer27H that senses itsoutput voltage through the auxiliary winding. A threshold on the CONT pin detects the OVPcondition and stops the IC operation. This protection has an auto-restart behavior.3.2Load transientsThe following figures show the behavior of the outputs during load transients. Each imageshows the transition from 20 % to 100 % of rated current and vice versa for a single outputvoltage. The current slope is 0.5 A/µs for all the current variations.Figure 11. Load transient on 12 V outputDoc ID 17402 Rev 217/49
Complete systemAN3203Figure 12. Load transient on 5 V outputFigure 13. Load transient on 3.3 V output3.3Standby operationWhen the PS ON is not high, the system is in standby mode. Good performance is obtainedthanks to the VIPer27H high voltage converter. Efficiency and no-load consumption valuesare shown in the next chapter.18/49Doc ID 17402 Rev 2
AN3203Electrical performance4Electrical performance4.1Efficiency measurement and no-load consumptionThe efficiency measurements taken at the two nominal voltages are seen in the followingtables. The 5 V SB output was unloaded during these measurements.Table 1.Efficiency @ 115 VrmsLoad 12 V @load[A] 5 V @load[A]20 %12.132.7025.022.4093.3325 %12.133.3745.0193.00850 %12.136.7495.01275 %12.1310.122100 %12.1213.5Table 2. 3.3 V @load[A]Pout [W]Pin [W]Eff [%]1.650.19658.585.81 %3.3292.00462.69571.9787.11 %6.0073.3253.999125.27140.2289.34 %5.0039.0063.3186.008187.77211.1988.91 %4.99612.0033.3138.001250.09285.4187.63 %Pout [W]Pin [W]Eff [%]Efficiency @ 230 VrmsLoad 12 V @load[A] 5 V @load[A] 3.3 V @load[A]20 %12.142.7015.0192.4083.3291.59950.19958.6285.63 %25 %12.143.3745.0183.0083.3282.00362.72071.5287.70 %50 %12.136.7545.0116.0063.3233.998125.31138.0790.76 %75 %12.1210.1225.0049.0063.3186.008187.68207.4990.45 %100 %12.1213.54.99712.0023.3138.001250.10279.6689.43 %The 80 PLUS program fixes several efficiency levels that describe how energy-efficient acomputer power supply is. The program defines the minimum efficiency requirements at 20%, 50 %, 100 % of rated load and a minimum power factor requirement.According to the program a power supply could be classified in 4 or 5 levels:Table 3.Note:80 PLUS program efficiency levels (115Vac)LevelEff @ 20 %Eff @ 50 %Eff @ 100 %PF (@ load %)80 PLUS 80 % 80 % 80 % 0.9 @ 100 %80 PLUS Bronze 82 % 85 % 82 % 0.9 @ 50 %80 PLUS Silver 85 % 88 % 85 % 0.9 @ 50 %80 PLUS Gold 87 % 90 % 87 % 0.9 @ 50 %80 PLUS Platinum 90 % 92 % 89 % 0.95 @ 50 %This table refers to power supplies for desktops, workstations, and non-redundant serverapplications with 115 Vac mainsDoc ID 17402 Rev 219/49
Electrical performanceTable 4.Note:AN320380 PLUS program efficiency levels (230 Vac)LevelEff @ 20%Eff @ 50%Eff @ 100%PF (@ load%)80 PLUS Bronze 81% 85% 81% 0.9 @ 50%80 PLUS Silver 85% 89% 85% 0.9 @ 50%80 PLUS Gold 88% 92% 88% 0.9 @ 50%80 PLUS Platinum 90% 94% 91% 0.95 @ 50%This table refers to power supplies for redundant, data center applications with 230VacmainsThis demonstration board is compliant with the 80 PLUS Silver specifications (for PF dataplease refer to Table 9). Since this is basically a desktop PC power supply, the tests wereperformed at 115 Vac. Certification report and other details can be found on the 80 PLUS web site.Similar levels of efficiency and power factor are defined also by the Climate SaversComputing Initiative. According to the measurements carried out, the demonstration boardis compliant with “Climate Savers Computing Silver” level.Table 5.Climate Savers Computing Initiative (for multi-output iencyPFEfficiencyPF20 %82 %0.885 %0.887 %0.850 %85 %0.988 %0.990 %0.9100 %82 %0.9585 %0.9587 %0.95Table 6 shows the no-load consumption. These values are taken with the signal PS ONkept low, therefore only the auxiliary stage is active and only the 5 V SB output is present.The board showed very good values (below 200 mW over the whole input voltage range),especially when considering that the inactive stages have a certain residual consumption(only the voltage dividers in the input stage waste about 100 mW @ 230 Vac).Table 6.No-load consumptionVin [Vac]90115135180230264Pin [mW]597082113161199Figure 14 and Figure 15 show the graph of the efficiency vs. output power at the twonominal input voltages while Figure 16 shows the graph of the input power vs. input voltagewith no load applied. It is clearly visible that the power supply is compliant with the 80PLUS SILVER specification and it is very close to the GOLD one.20/49Doc ID 17402 Rev 2
AN3203Electrical performanceFigure 14. Efficiency vs. O/P power @ 115 VacFigure 15. Efficiency vs. O/P power @ 230 VacFigure 16. No-load consumptionDoc ID 17402 Rev 221/49
Electrical performanceAN3203Some measurements with low output loads were also taken. They refer only to the operationof
demonstration board Introduction . transformer has two secondary windings with a center tap connected to the secondary ground. The other ends are connected to the sources of MOSFETs Q201 and Q202, which replace output diodes in order to
