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L.D. COLLEGE OF ENGINEERING,AHMEDABADLab ManualForDigital Logic DesignB.E. Semester IIIElectronics & Communication DepartmentSima Gosai7/16/2012NAME .CLASS .ENROLLMENT NO. BATCH LAB PARTNERS .
USEFUL 6741077410974173741747473747474757476Description of ICQuad 2 input NAND GATEQuad 2input NAND Gate (open collector)Quad 2 input NOR GateQuad 2 input NOR Gates (open collector)Hex InvertsQuad 2 input AND GateDual 4 input AND Gate8 input NAND GateQuad 2 input OR GateQuad 2 input EX-OR GateDual J-K Flip FlopDual J-K Flip Flop with Set and ResetQuad D Flip FlopHex D Flip FlopDual Master-Slave J-K Flip FlopDual D Flip FlopQuad Bi-stable latchDual J-K Flip Flop with Preset and Clear
Useful IC Pin detail7400(Quad 2 Input NAND)7402(Quad 2 Input NOR)7404 Hex Inverter (NOT)
7408(Quad 2 Input AND)7432 (Quad 2 Input OR)7486(Quad 2 Input EX-OR)
7411(3-i/p AND)7410(3-i/p NAND)7420(4-i/p NAND)7485 (4-Bit Magnitude Comparator)
7476 (Dual J-K Master-Slave Flip-Flop with Preset & Clear)
Experiment No:Date: / /STUDY OF LOGIC GATES AND VERIFY THEIR TRUTH TABLES.Aim: - Verification and interpretation of truth tables for AND, OR, NOT, NAND, NORExclusive OR (EX-OR), Exclusive NOR (EX-NOR) Gates.APPARATUS REQUIRED:SL No.1.2.3.4.5.6.7.8.COMPONENT SPECIFICATIONAND GATEIC 7408OR GATEIC 7432NOT GATEIC 7404NAND GATE 2 I/PIC 7400NOR GATEIC 7402X-OR GATEIC 7486IC TRAINER KITPATCH CORD-QTY1111111As perRequiredTHEORY:Logic gates are electronic circuits which perform logical functions on one or more inputs toproduce one output. There are seven logic gates. When all the input combinations of a logic gateare written in a series and their corresponding outputs written along them, then this input/ outputcombination is called Truth Table.OR, AND and NOT are basic gates. NAND, NOR are known as universal gates. Various gatesand their working is explained here.AND GATE:The AND gate performs a logical multiplication commonly known as AND function. The outputis high when both the inputs are high. The output is low level when any one of the inputs is low.OR GATE:The OR gate performs a logical addition commonly known as OR function. The output is highwhen any one of the inputs is high. The output is low level when both the inputs are low.NOT GATE:The NOT gate is called an inverter. The output is high when the input is low. The output is lowwhen the input is high.
NAND GATE:The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low andany one of the input is low .The output is low level when both inputs are high.NOR GATE:The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. Theoutput is low when one or both inputs are high.X-OR GATE:The output is high when any one of the inputs is high. The output is low when both the inputs arelow and both the inputs are high.PROCEDURE:ORANDGATE1. Connect the trainer kit to ac power supply.2. Connect the inputs of any one logic gate to the logic sources and its output to the logicindicator.3. Apply various input combinations and observe output for each one.4. Verify the truth table for each input/ output combination.5. Repeat the process for all other logic gates.6. Switch off the ac power supply.SYMBOLFUNCTIONOBSERVATIONTRUTH TABLE
CONCLUSION:EX-NOREX-ORNORNANDNOT
Experiment No:Date: / /IMPLEMENT BOOLEAN FUNCTION USING AOI LOGIC.Aim: - A. Implement Exclusive-OR gate using AOI logic.B. Implement Boolean function F xy x’y’ y’z using AOI logicAPPARATUS REQUIRED:SL No.1.2.3.4.5.COMPONENTAND GATEOR GATENOT GATEIC TRAINER KITSPECIFICATIONIC 7408IC 7432IC 7404-PATCH CORD-QTY1111As perRequiredTHEORY:A binary variable can take the value of 0 or 1. A Boolean function is an expression formed withbinary variables, the two binary operators OR and AND, and unary operator NOT, parentheses,and an equal sign. For a given value of the variables, the function can be either 0 or 1.Boolean function represented as an algebraic expression may be transformed from an algebraicexpression into a logic diagram composed of AND, OR, and NOT gates. . Every Booleanfunction can be realized by a And-Or-Not gates i.e. using AOI logicLOGIC DIAGRAM -A (For F x’y xy’)LOGIC DIAGRAM -B (For F xy x’y’ y’z)
PROCEDURE:1.2.3.4.5.6.Connect the trainer kit to ac power supply.Verify the gates and make connections as per circuit diagram-A.Apply various input combinations and observe output for each one.Verify the truth table for each input/ output combination.Repeat the process for circuit diagram-B.Switch off the ac power supply.TRUTH TABLE:FOR AINPUTxOUTPUTFyFOR BxCONCLUSION:INPUTyzOUTPUTF
Experiment No:Date: / /REALIZATION OF GATES USING UNIVERSAL GATESAim: - (A) To construct NOT, AND, OR, Exclusive OR (EX-OR), Exclusive NOR (EX-NOR)logic gates using only NAND gates.(B) To construct NOT, AND, OR, Exclusive OR (EX-OR), Exclusive NOR (EX-NOR)logic gates using only NOR gates.APPARATUS REQUIRED:SL No.COMPONENT SPECIFICATION1. NAND GATE 2 I/PIC 74002. NOR GATE 2 I/PIC 74023. IC TRAINER KIT4.PATCH CORD-QTY111As perRequired(A) NAND as a Universal gate:THEORY:NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate. So itsoutput is complement of the output of an AND gate. This gate can have minimum two inputs,output is always one. By using only NAND gates, we can realize all logic functions: AND, OR,NOT, X-OR, X-NOR, NOR. So this gate is also called universal gate.1. NAND gate as NOT gate:A NOT produces complement of the input. It can have only one input, tie the inputs of a NANDgate together. Now it will work as a NOT gate. Its output isY (A.A)’ (A)’2. NAND gates as AND gate:A NAND produces complement of AND gate. So, if the output of a NAND gate is inverted,overall output will be that of an AND gate.Y ((A.B)’)’ (A.B)
3. NAND gates as OR gate:From DeMorgan’s theorems: (A.B)’ A’ B’. Similarly, (A’.B’)’ A’’ B’’ A BSo, give the inverted inputs to a NAND gate, obtain OR operation at output.4. NAND gates as EX-OR gate:The output of a two input EX-OR gate is given by: Y A’B AB’. EX-OR gate can beimplemented using four NAND gates as follows.Gate No.Inputs1A, B2A, (AB)’3(AB)’, B4(A (AB)’)’, (B (AB)’)’Output(AB)’(A (AB)’)’(B (AB)’)’A’B AB’Now the ouput from gate no. 4 is the overall output of the configuration.YSo Y ((A (AB)’)’ (B (AB)’)’)’(A(AB)’)’’ (B(AB)’)’’(A(AB)’) (B(AB)’)(A(A’ B)’) (B(A’ B’))(AA’ AB’) (BA’ BB’)( 0 AB’ BA’ 0 )AB’ BA’AB’ A’B5. NAND gates as EX-NOR gateEX-NOR gate is actually EX-OR gate followed by NOT gate. So give the output of EX-OR gateto a NOT gate, overall ouput is that of an EX-NOR gate.Y AB A’B’PROCEDURE:(i)(ii)(iii)(iv)(v)Verify the gates and connect the NAND gates as per logic diagrams (A) for any ofthe logic functions to be realised.Connect Pin-14 of all ICs to 5V and Pin-7 to ground.Feed the logic 0 (0V) or 1(5V) in different combinations at the inputs A & Baccording to truth table.Observe and note down the output readings for Y for different combinations ofinputs and verify the truth table for input/output combinationRepeat the process for all logic functions/gates.
LOGIC DIAGRAMS (A):OBSERVATION TABLE (A):1. NAND gate as NOT gate:AY2. NAND gates as AND gate:ABYABY3. NAND gates as OR gate:
4. NAND gates as EX-OR gate:ABYABY5. NAND gates as EX-NOR gateCONCLUSION (A):
(B) NOR as a Universal gate:THEORY:NOR gate is actually a combination of two logic gates: OR gate followed by NOT gate. So itsoutput is complement of the output of an OR gate. This gate can have minimum two inputs,output is always one. By using only NOR gates, we can realize all logic functions: AND, OR,NOT, X-OR, X-NOR, NAND. So this gate is also called universal gate.1. NOR gate as NOT gate:A NOT produces complement of the input. It can have only one input, tie the inputs of a NORgate together. Now it will work as a NOT gate. Its output isY (A A)’ (A)’2. NOR gates as OR gate:A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted, overalloutput will be that of an OR gate.Y ((A B)’)’ (A B)3. NOR gates as AND gate:From DeMorgan’s theorems: (A B)’ A’. B’. Similarly, (A’ B’)’ A’’. B’’ A .BSo, give the inverted inputs to a NOR gate, obtain AND operation at output.4. NOR gates as EX-NOR gate:The output of a two input EX-NOR gate is given by: Y AB A’B’. EX-NOR gate can beimplemented using four NOR gates as follows.Gate No.1234InputsA, BA, (A B)’(A B)’, B(A (A B)’)’, (B (A B)’)’Output(A B)’(A (A B)’)’(B (A B)’)’AB A’B’Now the ouput from gate no. 4 is the overall output of the configuration.
YSoY ((A (A B)’)’ (B ( A B)’)’)’(A (A B)’)’’.(B (A B)’)’’(A (A B)’).(B (A B)’)(A A’B’).(B A’B’)(A A’).(A B’).(B A’)(B B’)1.(A B’).(B A’).1(A B’).(B A’)A.(B A’) B’.(B A’)AB AA’ B’B B’A’AB 0 0 B’A’AB B’A’AB A’B’5. NOR gates as EX-OR gateEX-OR gate is actually EX-NOR gate followed by NOT gate. So give the output of EX-NORgate to a NOT gate, overall ouput is that of an EX-OR gate.Y A’B AB’PROCEDURE:(i)(ii)(iii)(iv)(v)Verify the gates and connect the NOR gates as per logic diagrams (B) for any ofthe logic functions to be realised.Connect Pin-14 of all ICs to 5V and Pin-7 to ground.Feed the logic 0 (0V) or 1(5V) in different combinations at the inputs A & Baccording to truth table.Observe and note down the output readings for Y for different combinations ofinputs and verify the truth table for input/output combinationRepeat the process for all logic functions/gates.
LOGIC DIAGRAMS (B):OBSERVATION TABLE (B):1. NOR gate as NOT gate:AY2. NOR gates as OR gate:ABYABY3. NOR gates as AND gate:
4. NOR gates as EX-NOR gate:ABYABY5. NOR gates as EX-OR gateCONCLUSION (B) :
Experiment No:Date: / /VERIFICATION OF K-MAP.Aim: - Simplify the Boolean function F(w, x, y, z) Σ (0, 1,2,4,5,6,8,9, 12, 13, 14) using 4variable K-Map, implement it and verify it using truth-table.APPARATUS REQUIRED:SL No.1.2.3.4.5.6.7.8.COMPONENT SPECIFICATIONAND GATEIC 7408OR GATEIC 7432NOT GATEIC 7404NAND GATE 2 I/PIC 7400NOR GATEIC 7402X-OR GATEIC 7486IC TRAINER KITPATCH CORD-QTY1111111As perRequiredTHEORY:The complexity of the digital logic gates that implement a Boolean function is directly related tothe complexity of the algebraic expression from which the function is implemented. Although thetruth table representation of a function is unique, expressed algebraically, it can appear in manydifferent forms. Boolean functions may be simplified by algebraic means. However, thisprocedure of minimization is awkward because it lacks specific rules to predict each succeedingstep in the manipulative process. The map method provides a simple straightforward procedurefor minimizing Boolean functions. This method may be regarded either as a pictorial form of atruth table or as an extension of the Venn diagram. The map method, first proposed by Veitch andmodified by Karnaugh, is also known as the "Veitch diagram" or the "Karnaugh map."The map is a diagram made up of squares. Each square represents one minterm. Since anyBoolean function can be expressed as a sl1m of minterms, it follows that a Boolean function isrecognized graphically in the map from the area enclosed by those squares whose min terms areincluded in the function. In fact, the map presents a visual diagram of all possible ways a functionmay be expressed in a standard form. By recognizing various patterns, the user can derivealternative algebraic expressions for the same function, from which he can select the simplest one.We shall assume that the simplest algebraic expression is anyone in a sum of products or productof sums that has a minimum number of literals. (This expression is not necessarily unique.)The map for Boolean functions of four binary variables has 16 minterms and the square isassigned to each. The rows and columns are numbered in a reflected-code sequence, with onlyone digit changing value between two adjacent rows or columns. The minterm corresponding toeach square can be obtained from the concatenation of the row number with the column number.For example, the numbers of the third row (11) and the second column (01), when concatenated,
give the binary number 1101, the binary equivalent of decimal 13. Thus, the square in the thirdrow and second column represents minterm m13.PROCEDURE:(i)(ii)(iii)(iv)(v)(vi)Simplify the given Boolean function using 4-variable K-MapImplement simplified Boolean function using logic gates.Verify the gates and make connections as per the logic diagram.Connect Pin-14 of all ICs to 5V and Pin-7 to ground.Feed the logic 0 (0V) or 1(5V) in different combinations at the inputs w, x, y, andz according to truth table.Observe and note down the output readings for F for different combinations ofinputs and verify the truth table for input/output combinationF(w, x, y, z) Σ (0,1,2,4,5,6,8,9, 12, 13, 14)TRUTH TABLE REPRESENTATION OF THE 0110011001101010101010101011110111011001110
SIMPLIFICATION USING 4-VARIABLE K-MAPSimplified Boolean function F LOGIC DIAGRAM OF SIMPLIFIED BOOLEAN FUNCTION
OBSERVATION TABLE:wCONCLUSION:xyzF
Experiment No:Date: / /ADDERAim: - To design and construct half adder, full adder using logic gates and verify the truth table.APPARATUS REQUIRED:Sr. No.1.2.3.4.5.6.COMPONENTAND GATEX-OR GATENOT GATEOR GATEIC TRAINER KITPATCH CORDSPECIFICATIONIC 7408IC 7486IC 7404IC 7432-QTY.11111As perRequiredTHEORY:HALF ADDER:A half adder has two inputs for the two bits to be added and two outputs one from the sum ‘ S’and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a carrysignal from the addition of the less significant bits sum from the X-OR Gate the carry out fromthe AND gate.FULL ADDER:A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of threeinputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot doso. In full adder sum output will be taken from X-OR Gate, carry output will be taken from ORGate.
LOGIC DIAGRAM:HALF ADDERTRUTH TABLE:AK-Map for SUM:SUM A’B AB’BCARRYSUMK-Map for CARRY:CARRY AB
LOGIC DIAGRAM:FULL ADDER:FULL ADDER USING TWO HALF ADDER:TRUTH TABLE:ABCCARRYK-Map for SUM:SUM A’B’C A’BC’ ABC’ ABCSUM
K-Map for CARRY:CARRY AB BC ACPROCEDURE:(vi)(vii)Verify the gates and make Connections as per logic diagram.Connect Pin-14 of all ICs to 5V and Pin-7 to ground.(viii) Apply various combinations of inputs to A,B,C according to truth table.(ix) Observe and note down the output readings for SUM and CARRY for differentcombinations of inputs and verify the truth table.CONCLUSION:
Experiment No:Date: / /SUBTRACTORAIM: To design and construct half subtractor and full subtractor circuits using logic gates andverify the truth table.APPARATUS REQUIRED:Sr. No.1.2.3.4.5.6.COMPONENTAND GATEX-OR GATENOT GATEOR GATEIC TRAINER KITPATCH CORDSPECIFICATIONIC 7408IC 7486IC 7404IC 7432-QTY.11111As perRequiredTHEORY:HALF SUBTRACTOR:The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two inputand two outputs. The outputs are difference and borrow. The difference can be applied using XOR Gate, borrow output can be implemented using an AND Gate and an inverter.FULL SUBTRACTOR:The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor thelogic circuit should have three inputs and two outputs. The two half subtractor put together givesa full subtractor .The first half subtractor will be C and A B. The output will be difference outputof full subtractor. The expression AB assembles the borrow output of the half subtractor and thesecond term is the inverted difference output of first X-OR.
LOGIC DIAGRAM:HALF SUBTRACTORTRUTH TABLE:ABBORROW DIFFERENCEK-Map for DIFFERENCE:DIFFERENCE A’B AB’K-Map for BORROW:BORROW A’B
LOGIC DIAGRAM:FULL SUBTRACTOR:FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:TRUTH TABLE:ABCBORROW DIFFERENCEK-Map for Difference:DIFFERENCE A’B’C A’BC’ AB’C’ ABC
K-Map for Borrow:BORROW A’B BC A’CPROCEDURE:(i)(ii)(iii)(iv)Verify the gates and make connections as per logic diagram.Connect Pin-14 of all ICs to 5V and Pin-7 to ground.Apply various combinations of inputs to A,B,C according to truth table.Observe and note down the output readings for SUM and CARRY for differentcombinations of inputs and verify the truth table.CONCLUSION:
Experiment No:Date: / /BCD TO EXCESS-3 CODE CONVERTERAIM: To Design and Implement BCD TO EXCESS-3 CONVERTER and verify the truth tableAPPARATUS REQUIRED:Sr. No.1.2.3.4.5.6.COMPONENTAND GATEX-OR GATENOT GATEOR GATEIC TRAINER KITSPECIFICATIONIC 7408IC 7486IC 7404IC 7432-PATCH CORD-QTY.11111As perRequiredTHEORY:The availability of large variety of codes for the same discrete elements of informationresults in the use of different codes by different systems. A conversion circuit must be insertedbetween the two systems if each uses different codes for same information. Thus, code converteris a circuit that makes the two systems compatible even though each uses different binary code.Binary Coded Decimal:Binary Coded Decimal is a method of using binary digits to represent the decimal digits 0through 9. It is possible to assign weights to the binary bits according to their positions. Theweights in the BCD code are 8, 4, 2 and 1. Ex: (137)10 - BCD equivalent (0001 0011 0111)2.Excess-3 Code:This is an un-weighted code. Its code assignment is obtained from the corresponding value ofBCD after the addition of (0011)2.BCD to Excess-3 (or) Excess-3 to BCD:Since each code uses four bits to represent a decimal digit, there must be four inputs and fouroutput variables. The input variable are designated as B3, B2, B1, B0 and the output variablesare designated as E3, E2, E1, E0 in the truth table. Four binary variables have sixteen differentinput combinations, only ten of the input combinations are listed in the truth table. The six bitcombinations not listed for the input variables are don’t care combination. The Booleanfunctions are obtained from K-Map for each output variable. The combinational logic fort h e code converters are designed according the Boolean expressions from K -Map
simplification. The Boolean expressions from the K-Map are shown below. Each one of the fourmaps represents one of the four outputs of the circuit as a function of the four input variables.A two-level logic diagram may be obtained directly from the Boolean expressions derived by themaps. These are various other possibilities for a logic diagram that implements this circuit.PROCEDURE:(i)Determine number of available input variables and required output variables andassign letter symbols to them.(ii)Derive appropriate truth table.(iii) Obtain simplified Boolean function for each output variable.(iv)Draw logic diagram.(v)Verify the gates.(vi)Make connections as per the logic diagram.(vii) Connect Pin-14 of all ICs to 5V and Pin-7 to ground.(viii) Apply various combinations of inputs to B3, B2, B1, B0 for BCD according totruth table.(ix) Observe and note down the output readings for E3, E2, E1, E0 for differentcombinations of inputs for corresponding Excess-3.(x) Verify the truth table.
TRUTH TABLE: BCD input Excess – 3 output 100001xxxxxx1001100110xxxxxx1010101010xxxxxx
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGK-Map for E3:E3 B3 B2 (B0 B1)K-Map for E2:35
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGK-Map for E1:K-Map for E0:36
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGLOGIC DIAGRAM:BCD TO EXCESS-3 CONVERTOROBSERVATION TABLE: BCD inputB3B2 B1B0Excess – 3 outputE337E2E1 E0
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGCONCLUSION:38
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGExperiment No:Date: / /BINARY TO GRAY /GRAY TO BINARY CODE CONVERTERAIM: To Design & implement 4-bit Binary to gray code converter/ 4-bit Gray toBinary code converter and verify the truth table.APPARATUS REQUIRED:Sr. No.COMPONENT1.X-OR GATE2.IC TRAINER KIT3.PATCH CORDSPECIFICATIONIC 7486-QTY.11As perRequiredTHEORY:Gray Code:To obtain a different gray code, one can start with any bit information and proceed toobtain the next bit combination by changing only one bit from 0 to 1 (or) 1 to 0 inany desired random fashion provided any two numbers do not have identical codeassignments.Binary to Gray (or) Gray to Binary conversion:To convert from binary code to Gray code, the input lines must supply the bitcombination of elements as specified by the code and the output lines generate thecorresponding bit combination of code.In the case of binary to gray conversion, the input variable are designated as B3, B2, B1,B0 and the output variables are designated as G3, G2, G1, G0. While in the case of grayto binary conversion, the input variable are designated as G3, G2, G1, G0 and the outputvariables are designated as B3, B2, B1, B0 in the truth table . Four binary variables havesixteen different input combinations. The Boolean functions are obtained from K-Mapfor each output variable. The combinational logic for t h e code converters aredesigned according the Boolean expressions from K -Map simplification. TheBoolean expressions from the K-Map are shown below. Each one of the four mapsrepresents one of the four outputs of the circuit as a function of the four input variables.39
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGBinary to Gray Code Conversion Steps:The example shows the steps involved in conversion of a binary code to its graycode. Binary code taken for the example is 1011.BINARYB3B2B1B01011 GRAY 1110G3G2G1G0In the conversion process the most significant bit (MSB) of the binary code istaken as the MSB of the Gray code. The bit positions G2, G1 and G0 isobtained by adding (B3, B2), (B2, B1) and (B1, B0) respectively, ignoring thecarry generated. From the K-Map simplification for binary to Gray codeconversion the following Boolean expressions are obtained,G3 B3G2 B3B2G1 B2B1G0 B1B0PROCEDURE:(i)(ii)(iii)(iv)(v)(vi)Assign letter symbols to each input variables and output variables asmentioned above for both the code converters (Binary-Gray/Gray-Binary).Derive appropriate truth table for both the code converters.Obtain simplified Boolean function for each output variable for both thecode converters.Draw logic diagrams.Verify the gates.Make connections as per the logic diagram of Binary to Gray codeconverter.40
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF onnect Pin-14 of IC to 5V and Pin-7 to ground.Apply various combinations of inputs to B3, B2, B1, and B0 according totruth table.Observe and note down the output readings for G3, G2, G1, and G0 for allthe 16 combinations of the inputs for corresponding Gray code.Verify the truth table.Now make connections as per the logic diagram of Gray to Binary codeconverter.Apply various combinations of inputs to G3, G2, G1, and G0 according totruth table.Observe and note down the output readings for B3, B2, B1, and B0 for allthe 16 combinations of the inputs for corresponding Binary code.Verify the truth table.BINARY TO GRAY CODE CONVERTORTRUTH TABLE: Binary input Gray code output 1111111100000011110000111100011001100110011041
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGK-Map for G3:K-Map for G2:G3 B3K-Map for G1:K-Map for G0:42
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGLOGIC DIAGRAM:GRAY CODE TO BINARY CONVERTORTRUTH TABLE: Gray Code Binary Code 1111000011110011001100110011010101010101010143
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGK-Map for B3:B3 G3K-Map for B2:44
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGK-Map for B1:K-Map for B0:45
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGLOGIC DIAGRAM:46
DIGITAL LOGIC DESIGN LAB MANUALL.D. COLLEGE OF ENGINEERINGOBSERVATION TABLE:G3 G2 G1 G0 B3 B2 B1 B0G3 G2 G1 G0 B3 B2 B1 B0CONCLUSION:47
2. Connect the inputs of any one logic gate to the logic sources and its output to the logic indicator. 3. Apply various input combinations and observe output for each one. 4. Verify the truth table for each input/ output combination. 5. Repeat the process for all other
