Transcription
FIR CompilerUser Guide101 Innovation DriveSan Jose, CA 95134www.altera.comSoftware Version:Document Date:9.1November 2009
Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all otherwords and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and othercountries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use ofany information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version ofdevice specifications before relying on any published information and before placing orders for products or services.UG-FIRCOMPILER-9.1
ContentsChapter 1. About This CompilerRelease Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5Performance and Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8Chapter 2. Getting StartedDesign Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1DSP Builder Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1MegaWizard Plug-In Manager Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2Parameterize the MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3Generate the MegaCore Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8Simulating in ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8Simulating in MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9Simulating in Third-Party Simulation Tools Using NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9Compile the Design and Program a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9Chapter 3. Parameter SettingsSpecifying the Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1Using the FIR Compiler Coefficient Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2Loading Coefficients from a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–6Analyzing the Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8Specify the Input and Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9Specify the Architecture Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11Resource Estimates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16Filter Design Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16Chapter 4. Functional DescriptionFIR Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1Number Systems and Fixed-Point Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1Generating or Importing Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1Coefficient Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2Symmetrical Architecture Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3Symmetrical Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3Coefficient Reloading and Reordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4Structure Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6Multicycle Variable Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6Parallel Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6Serial Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7Multibit Serial Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7Multichannel Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8Interpolation and Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 November 2009 Altera CorporationFIR Compiler User Guide
ivContentsImplementation Details for Interpolation and Decimation Structures . . . . . . . . . . . . . . . . . . . . . 4–10Availability of Interpolation and Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11Half-Band Decimation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12Symmetric-Interpolation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12Simulation Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13Avalon Streaming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13Avalon-ST Data Transfer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14Packet Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17Reset and Global Clock Enable Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18Single Rate Filter Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–18Interpolation Filter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20Decimation Filter Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21Coefficient Reloading Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–26Appendix A. FIR Compiler Supported Device StructuresSupported Device Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1HardCopy II Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3Compiling HardCopy II Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3Additional InformationRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2FIR Compiler User Guide November 2009 Altera Corporation
1. About This CompilerRelease InformationTable 1–1 provides information about this release of the Altera FIR Compiler.Table 1–1. FIR Compiler Release InformationItemDescriptionVersion9.1Release DatefNovember 2009Ordering CodeIP-FIRProduct ID0012Vendor ID6AF7For more information about this release, refer to the MegaCore IP Library Release Notesand Errata.Altera verifies that the current version of the Quartus II software compiles theprevious version of each MegaCore function. The MegaCore IP Library Release Notesand Errata report any exceptions to this verification. Altera does not verifycompilation with MegaCore function versions older than one release.Device Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families, as described below: Full support means the MegaCore function meets all functional and timingrequirements for the device family and may be used in production designs Preliminary support means the MegaCore function meets all functionalrequirements, but may still be undergoing timing analysis for the device family; itmay be used in production designs with caution.Table 1–2 shows the level of support offered by the FIR Compiler to each Alteradevice family.Table 1–2. Device Family Support(Part 1 of 2)Device Family November 2009SupportArria II GXPreliminaryArria GXFullCycloneFull Cyclone IIFullCyclone IIIFullCyclone III LSPreliminaryCyclone IVPreliminaryAltera CorporationFIR Compiler User Guide
1–2Chapter 1: About This CompilerFeaturesTable 1–2. Device Family Support (Continued) (Part 2 of 2)Device FamilySupportHardCopy IIFullHardCopy IIIPreliminaryHardCopy IV EPreliminaryHardCopy IV GXPreliminaryStratix FullStratix IIFullStratix II GXFullStratix IIIFullStratix IVPreliminaryStratix GXFullOther device familiesNo support FeaturesThe Altera FIR Compiler implements a finite impulse response (FIR) filter MegaCorefunction and supports the following features: FIR Compiler User GuideThe following hardware architectures are supported to enable optimal trade- offsbetween logic, memory, DSP blocks, and performance: Fully parallel distributed arithmetic Fully serial distributed arithmetic Multibit serial distributed arithmetic Multicycle variable structures Exploit maximal efficiency designs as a result of FIR Compiler hardwareoptimizations such as interpolation, decimation, symmetry, decimation half-band,and time sharing. Easy system integration using Avalon Streaming (Avalon-ST) interfaces. Precision control of chip resource utilization: Logic cells, M512, M4K, M-RAM, MLAB, M9K, or M144K for data storage. M512, M4K, M9K, MLAB or logic cells for coefficient storage. Includes a resource estimator. Support for run-time coefficient reloading capability and multiple coefficient sets. Includes a built-in coefficient generator to enable efficient design spaceexploration. User-selectable output precision via rounding and saturation. DSP Builder ready. November 2009 Altera Corporation
Chapter 1: About This CompilerGeneral Description1–3General DescriptionThe Altera FIR Compiler provides a fully integrated finite impulse response (FIR)filter development environment optimized for use with Altera FPGA devices.You can use the IP Toolbench interface to implement a variety of filter architectures,including fully parallel, serial, or multibit serial distributed arithmetic, and multicyclefixed/variable filters. The FIR Compiler includes a coefficient generator.Many digital systems use signal filtering to remove unwanted noise, to providespectral shaping, or to perform signal detection or analysis. Two types of filters thatprovide these functions are finite impulse response (FIR) filters and infinite impulseresponse (IIR) filters. Typical filter applications include signal preconditioning, bandselection, and low-pass filtering.In contrast to IIR filters, FIR filters have a linear phase and inherent stability. Thisbenefit makes FIR filters attractive enough to be designed into a large number ofsystems. However, for a given frequency response, FIR filters are a higher order thanIIR filters, making FIR filters more computationally expensive.The structure of a FIR filter is a weighted, tapped delay line as shown in Figure 1–1.Figure 1–1. Basic FIR FilterxinZ -1C0ZC1-1Z-1C2ZC3-1TappedDelay LineCoefficientMultipliersAdder TreeyoutThe filter design process involves identifying coefficients that match the frequencyresponse specified for the system. These coefficients determine the response of thefilter. You can change which signal frequencies pass through the filter by changing thecoefficient values or adding more coefficients.Traditionally, designers have been forced to make a trade-off between the flexibility ofdigital signal processors and the performance of ASICs and application-specificstandard product (ASSPs) digital signal processing (DSP) solutions. The Altera DSPsolution reduces the need for this trade-off by providing exceptional performancecombined with the flexibility of FPGAs. November 2009Altera CorporationFIR Compiler User Guide
1–4Chapter 1: About This CompilerGeneral DescriptionFigure 1–2 compares the design cycle using a FIR Compiler MegaCore function with atraditional implementation.Figure 1–2. Design Cycle ComparisonFIR Compiler FlowTraditional FlowDefine & Design ArchitecturalBlocksDefine & Design ArchitecturalBlocksFIR FilterDesign6 WeeksFIR Filter Design1 DayDetermine BehavioralCharacteristics of FIR FilterSpecify Filter Characteristicsto FIR Compiler Megafunction(FIR Compiler Assists in Area/Speed Tradeoff)Calculate Filter Coefficients(MATLAB)Determine Hardware FilterArchitectureSimulateDesign Structural or SynthesizableFIR FilterSynthesize & Place & RouteSimulateSynthesize & Place & RouteArea/Speed TradeoffFigure 1–3 shows a typical DSP system that uses Altera MegaCore functions.Figure 1–3. Typical Modulator SystemOuter Encoding LayerInputDataFECReed SolomonEncoderConvolutionalInterleaverInner Coding pperFIR CompilerNLPFQNCOCompilerFIR CompilerNDACOutputDataLPFDSP processors have a limited number of multiply accumulators (MACs), and requiremany clock cycles to compute each output value (the number of cycles is directlyrelated to the order of the filter).FIR Compiler User Guide November 2009 Altera Corporation
Chapter 1: About This CompilerMegaCore Verification1–5A dedicated hardware solution can achieve one output per clock cycle. A fullyparallel, pipelined FIR filter implemented in an FPGA can operate at very high datarates, making FPGAs ideal for high-speed filtering applications.Table 1–3 compares resource usage and performance for different implementations ofa 120-tap FIR filter with a 12-bit data input bus.Table 1–3. FIR Filter Implementation Comparison (Note 1)DeviceClock Cycles toCompute ResultImplementationDSP processor1 MAC120FPGA1 serial filter121 parallel filter1Note to Table 1–3:(1) If you use the FIR Compiler to create a filter, you can also implement a variable filter in a FPGA that uses from 1to 120 MACs, and 120 to 1 clock cycles.The FIR Compiler speeds the design cycle by: Generating the coefficients needed to design custom FIR filters. Generating bit-accurate and clock-cycle-accurate FIR filter models (also known asbit-true models) in the Verilog HDL and VHDL languages and in the MATLABenvironment. Automatically generating the code required for the Quartus II software tosynthesize high-speed, area-efficient FIR filters of various architectures. Generating a VHDL testbench for all architectures.MegaCore VerificationBefore releasing an updated version of the FIR Compiler, Altera runs a comprehensiveregression test to verify its quality and correctness.All features and architectures are tested by sweeping all parameter options andverifying that the simulation matches a master functional model.Performance and Resource UtilizationThis section shows typical expected performance for a FIR Compiler MegaCorefunction using the Quartus II software, version 8.0 with Cyclone III, and Stratix IVdevices. All figures are given for a FIR filter with 97 taps, 8-bit input data, 14-bitcoefficients, and a target fMAX set to 1GHz.1Cyclone III devices use combinational look-up tables (LUTs) and logic registers;Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logicregisters.The resource and performance data was generated with the source ready signal(ast source ready) always driven high, as described in “Avalon StreamingInterface” on page 4–13. November 2009Altera CorporationFIR Compiler User Guide
1–6Chapter 1: About This CompilerPerformance and Resource UtilizationTable 1–4 shows performance figures
words and logos that are ide ntified as trademarks and/ or service marks are, unless noted ot herwise, the tradem arks and service marks of Altera Corporation in the U.S. and other countries. All other product or se
