Problem Solutions Chapter 2 - Usb

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Solutions Manual for Logic and Computer Design Fundamentals 5th Edition by Mano IBSN 9780133760637Full Download: ion-by-maProblem Solutions – Chapter 2CHAPTER 2 2016 Pearson Education, Inc.2-1.*a)XYZ X Y ZVerification of DeMorgan’s Theoremb)XYZXYZXYZX Y Z000011001011010011011011100011101011110011111100X YZ ( X Y ) ( X Z )The Second Distributive 1111100111111111111c)YZX YZX YX Z(X Y)(X Z)Ta histh nd woo eir is rkw r sa co pro isill le u vi prde o rse de otst f a s d s ecro n an o tey y p d le dth a a ly bye rt ss fo Uin o e rte f t ss th nitegr hi in eity s w g us d Sof or stu e o tatth k ( de f i ese in nt ns cow cl le tr por ud a uc yrkan ing rnin tors ighd on g. in t laiswDno the iss tea st p W em cher or in ingm ld aitt W tioed id n.eWeb)XXY YZ XZ XY YZ XZXYYZXZXY YZ XZXYYZXZXY YZ X Y XY XY X Y ( X Y X Y ) ( XY XY ) X (Y Y ) Y ( X X ) X Y1 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currentlyexist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.Full all chapters instant download please go to Solutions Manual, Test Bank site: downloadlink.org

Problem Solutions – Chapter 2b)AB BC AB BC 1 X Y Z X Y XZ YZ ( AB AB) ( BC BC ) B( A A) B (C C )B B 1c)Y XZ XY Y XY XZ (Y X )(Y Y ) XZ Y X XZ Y ( X X )( X Z ) X Y Zd)XY Y Z XZ XY YZ XY YZ ( X X ) XZ XY YZ XY XYZ XYZ XZ XY YZ XY (1 Z ) XYZ XZ XY YZ XY XZ (1 Y ) XY YZ XY XZ XY ( Z Z ) YZ XY XZ XYZ YZ (1 X )Ta histh nd woo eir is rkw r sa co pro isill le u vi prde o rse de otst f a s d s ecro n an o tey y p d le dth a a ly bye rt ss fo Uin o e rte f t ss th nitegr hi in eity s w g us d Sof or stu e o tatth k ( de f i ese in nt ns cow cl le tr por ud a uc yrkan ing rnin tors ighd on g. in t laiswDno the iss tea st p W em cher or in ingm ld aitt W tioed id n.eWeb) XY XZ (1 Y ) YZ XY XZ YZ2-3. a)ABC BCD BC CD B CD ABC ABC BC BCD BCD CD AB(C C ) BC ( D D) BC CD AB BC BC CD B AB CD B CDb)WY WYZ WXZ WXY WY WXZ XYZ XYZ (WY WXYZ ) (WXYZ WXYZ ) (WXYZ WXYZ ) (WXYZ WXY Z ) (WY WXYZ ) (WXYZ WXY Z ) (WXYZ WXYZ ) (WXYZ WXYZ ) WY WXZ (Y Y ) XYZ (W W ) XYZ (W W ) WY WXZ XYZ XYZc)AD AB CD BC ( A B C D)( A B C D) AD AB CD BC ( A D)( A B )(C D)( B C ) ( AB AD BD)( BC BD CD) ABCD ABCD ( A B C D)( A B C D ) ( A B C D )( A B C D )2 2016 Pearson Education, Inc. AD BD or AB F C AD( BD or AB)F BDXCX 0 X0 1 X 0B0 1 1 0XXXX 1AXX 0XDF B DF BDF ((X Y) or (X Z))(W Y Z)(W Y Z)((W X Z) or (W Y Z))8 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currentlyexist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Problem Solutions – Chapter 22-27.*X Y XY XYDual(X Y ) Dual( XY XY ) ( X Y )( X Y ) XY XY XY XY X Y2-28.ABCD AD AD ABCD ( A D)Note that X Y ( X Y ) XYLetting X ABCD and Y A D,We can observe from the map below or determine algebraically that XY is equal to 0.Ta histh nd woo eir is rkw r sa co pro isill le u vi prde o rse de otst f a s d s ecro n an o tey y p d le dth a a ly bye rt ss fo Uin o e rte f t ss th nitegr hi in eity s w g us d Sof or stu e o tatth k ( de f i ese in nt ns cow cl le tr por ud a uc yrkan ing rnin tors ighd on g. in t laiswDno the iss tea st p W em cher or in ingm ld aitt W tioed id n.eWeb)CA1111111B11DFor this situation,X Y ( X Y ) XY ( X Y ) 0 X YSo, we can write F ( A, B, C, D) X Y ABCD ( A D)ABDCF2-29.*The longest path is from input C or D.0.073 ns 0.073 ns 0.048 ns 0.073 ns 0.267 ns9 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currentlyexist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Problem Solutions – Chapter 22-30.a)b)c)01.02.03.04.05.06.07.08.09.0 ns2-31.a) t PHL-C, D to F 2t PLH 2 t PHL 2(0.36) 2(0.20) 1.12 nst PLH-C, D to F 2t PHL 2t PLH 2(0.20) 2(0.36) 1.12 nst pd 1.12 nst PHL-B to F 2t PHL t PLH 2(0.20) (0.36) 0.76 nsTa histh nd woo eir is rkw r sa co pro isill le u vi prde o rse de otst f a s d s ecro n an o tey y p d le dth a a ly bye rt ss fo Uin o e rte f t ss th nitegr hi in eity s w g us d Sof or stu e o tatth k ( de f i ese in nt ns cow cl le tr por ud a uc yrkan ing rnin tors ighd on g. in t laiswDno the iss tea st p W em cher or in ingm ld aitt W tioed id n.eWeb)t PLH-B to F 2t PHL t PLH 2(0.36) (0.20) 0.92 nst pd-B to F 0.76 0.92 0.84 nst PHL-A, B, C to F t PLH t PHL 0.36 0.20 0.56 nst PLH-A, B, C to F t PHL t PLH 0.20 0.36 0.56 nst pd-A, B, C to F 0.56 nsb) t pd-C, D to F 4 t pd 4(0.28) 1.12 nst pd-B to F 3 t pd 3(0.28) 0.78 nst pd-A, B, C to F 2 t pd 2(0.28) 0.56 nsc) For paths through an odd number of inverting gates with unequal gate tPHL and tPLH, path tPHL, tPLH, and tpd are different.For paths through an even number of inverting gates, path tPHL, tPLH, and tpd are equal.2-32.If the rejection time for inertial delays is greater than the propagation delay, then an output change can occur before itcan be predicted whether or not it is to occur due to the rejection time.For example, with a delay of 2 ns and a rejection time of 3 ns, for a 2.5 ns pulse, the initial edge will have alreadyappeared at the output before the 3 ns has elapsed at which whether to reject or not is to be determined.10 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currentlyexist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Problem Solutions – Chapter 22-33. a) The propagation delay is tpd max(tPHL 0.05, tPLH 0.10) 0.10 ns.a) The propagation delay istpd max(tPHL 0.05, tPLH 0.10) 0.10 ns.a) ThetPHLpulse, 0.05, 0.10) 0.10occurs:ns.Assuming that thegatepropagationis an inverter,delayfor aistpositiveoutputthet followingactuallypd max(Assuming that the gate is an inv, erterf ora positiv ePLHoutput pulse, the f ollowing actually occurs:Assuming that the gate is an inv, erterf or a positiv e output pulse, the f ollowing actually occurs:0.05 ns0.10 ns0.05 ns0.10 nsIf the input pulse is narrower than 0.05 ns, no output pulse occurs so the rejection time is 0.05 ns.If theinput pulseis narrower thethanf ollowing0.05 ns,results,no outputpulseoccursso the delayrejectiontimeTheresultingmodelwhichf erdifftimerombehav, ioris 0.05 ns.If the input pulseis narrowerthan0.05predictsns, no output pulseoccurs so the rejectionisthe0.05actualns. The gresults,whichferdiffromtheactualdelaybehavbut modelsrejectionbehav: delay behavior, but models the rejection behavior: : , iorpredicts the followingresults,thewhichdiffer fromtheior:actualbut models the rejection behav ior: :0.10 ns0.10 ns 0.10 ns0.10 nsTa histh nd woo eir is rkw r sa co pro isill le u vi prde o rse de otst f a s d s ecro n an o tey y p d le dth a a ly bye rt ss fo Uin o e rte f t ss th nitegr hi in eity s w g us d Sof or stu e o tatth k ( de f i ese in nt ns cow cl le tr por ud a uc yrkan ing rnin tors ighd on g. in t laiswDno the iss tea st p W em cher or in ingm ld aitt W tioed id n.eWeb)b) For a negative output pulse, the following actually occurs:b) For a negative output pulse, the following actually occurs:b) For a negative output pulse, the following actually occurs:0.05 ns0.15 ns 0.050.10ns ns0.10 ns0.15 nsThe model predicts the f ollowing results, whichf ersdif f rom the actual delay behav ior and f romThe model predicts the following results, which differs from the actual delay behavior and from the actual tsthefollowingresults,whichfersdiff rom the actual delay behav ior and f rombehavior:the actual rejection behavior:0.10 ns0.10 ns0.10 ns0.10 nsOverall, the model is inaccurate for both cases a and b, and provides a faulty rejectionmodel ftheor modelcase b.Using anforavbotherageofandt b,f ort provideswould improve rejectionthe delayOverall,is inaccuratecasesat andanda faultyPHLPLHpdOverall, the model is inaccurateforbothandb, singanaccuracythecasesmodelfor f orofcaseb. a Usingan e of tPHL and tPLH itapplications,buttherejectionpdaccuracy of the model for circuit applications, but the rejection model still fails.model still fails.2-34.*X1N1N2X2N6N3fN4X3N5X42-35.-- Figure 4-40: Structural VHDL Descriptionlibrary ieee;use ieee.std logic 1164.all;entity nand2 isport(in1, in2: in std logic;out1 : out std logic);end nand2;11 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currentlyexist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Problem Solutions – Chapter 2architecture concurrent of nand2 isbeginout1 not (in1 and in2);end architecture;library ieee;use ieee.std logic 1164.all;entity nand3 isport(in1, in2, in3 : in std logic;out1 : out std logic);end nand3;architecture concurrent of nand3 isbeginout1 not (in1 and in2 and in3);end concurrent;Ta histh nd woo eir is rkw r sa co pro isill le u vi prde o rse de otst f a s d s ecro n an o tey y p d le dth a a ly bye rt ss fo Uin o e rte f t ss th nitegr hi in eity s w g us d Sof or stu e o tatth k ( de f i ese in nt ns cow cl le tr por ud a uc yrkan ing rnin tors ighd on g. in t laiswDno the iss tea st p W em cher or in ingm ld aitt W tioed id n.eWeb)library ieee;use ieee.std logic 1164.all;entity nand4 isport(in1, in2, in3, in4: in std logic;out1 : out std logic);end nand4;-- The code above this point could be eliminated by using the library, func prims.library ieee;use ieee.std logic 1164.all;entity fig440 isport(X: in std logic vector(2 to 0);f: out std logic);end fig440;architecture structural 2 of fig440 iscomponent NAND2port(in1, in2: in std logic;out1: out std logic);end component;component NAND3port(in1, in2, in3: in std logic;out1: out std logic);end component;signal T: std logic vector(0 to 4);beging0: NAND2 port map (X(2),X(1),T(0));g1: NAND2 port map (X(2),T(0),T(1));g2: NAND2 port map (X(1),T(0),T(2));g3: NAND3 port map (X(1),T(1),T(2),T(3));g4: NAND2 port map (X(1),T(2),T(4));g5: NAND2 port map (T(3),T(4),f);end structural 2;F X0X 2 X 1X 2F X0X2 X1X012 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currentlyexist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Problem Solutions – Chapter 22-36.beginX D BCg0: beginNOT 1 port map (D, x1);Y A BCDX D BCY ABCDg1: AND 2map (B,C,mapx2);g0: portNOT 1port(D, x1);g2: NOR 2map (A,x1,mapx3); (B, C, x2);g1: portAND 2portg3: NAND 2port mapport(x1, x3,x4);g2: NOR 2map(A, x1, x3);g4: OR 2portmap(x1,x2,x5);g3: NAND 2 port map (x1, x3, x4);g4: portOR 2g5: AND 2mapport(x4, mapx5, X);(x1, x2, x5);g5: portAND 2portx5,mapg6: AND 2map (x3,Y); (x4, x5, X);g6: AND 2 port map (x3, x5, Y);end structural 1;end structural 1;2-37.2-38.*Ta histh nd woo eir is rkw r sa co pro isill le u vi prde o rse de otst f a s d s ecro n an o tey y p d le dth a a ly bye rt ss fo Uin o e rte f t ss th nitegr hi in eity s w g us d Sof or stu e o tatth k ( de f i ese in nt ns cow cl le tr por ud a uc yrkan ing rnin tors ighd on g. in t laiswDno the iss tea st p W em cher or in ingm ld aitt W tioed id n.eWeb)abacbcbacdfgbeginF (X and Z) or ((not Y) and Z);end;2-39.*X1N1N2X2N6N3fN4X3N5X413 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currentlyexist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Problem Solutions – Chapter 22-40.module circuit 4 50(A, B, C, D, X, Y);input A, B, C, D;output X, Y;wire n1, n2, n3, n4, n5;notgo(n1, D);nandg1(n4, n1, n3);andg2(n2, B, C),g3(X, n4, n5),g4(Y, n3, n5);org6(n3, n1, A);endmoduleTa histh nd woo eir is rkw r sa co pro isill le u vi prde o rse de otst f a s d s ecro n an o tey y p d le dth a a ly bye rt ss fo Uin o e rte f t ss th nitegr hi in eity s w g us d Sof or stu e o tatth k ( de f i ese in nt ns cow cl le tr por ud a uc yrkan ing rnin tors ighd on g. in t laiswDno the iss tea st p W em cher or in ingm ld aitt W tioed id n.eWeb)g5(n5, n1, n2);nor14 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currentlyexist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Solutions Manual for Logic and Computer Design Fundamentals 5th Edition by Mano IBSN 9780133760637Full Download: ion-by-maProblem Solutions – Chapter 22-41.module circuit 4 51(X, F);input [2:0]module circuit 4 51(X,F);X;outputF;input [2:0]X;output F;[0:4] T;nandnandg0(T[0],X[0],X[1]),g0(T [0],X[0],X[1]),g1(Tg1(T[1],X[0],T[0]),[1],X[0],T [0]),g2(Tg2(T[2],X[1],T[0]),[2],X[1],T [0]),g3(Tg3(T[3],X[2],T[1],T[2]),[3],X[2],T [1],T [2]),g4(T [4],X[2],T [2]),g4(T[4],X[2],T[2]),g5(F,T [3],T [4]);endmodule g5(F,T[3],T[4]);endmodule2-42.Ta histh nd woo eir is rkw r sa co pro isill le u vi prde o rse de otst f a s d s ecro n an o tey y p d le dth a a ly bye rt ss fo Uin o e rte f t ss th nitegr hi in eity s w g us d Sof or stu e o tatth k ( de f i ese in nt ns cow cl le tr por ud a uc yrkan ing rnin tors ighd on g. in t laiswDno the iss tea st p W em cher or in ingm ld aitt W tioed id n.eWeb)wire [0:4]wireT;abacbcbacd2-43.*fgmodule circuit 4 53(X, Y, Z, F);input X, Y, Z;output F;assign F (X & Z) (Z & Y);endmodule15 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currentlyexist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.Full all chapters instant download please go to Solutions Manual, Test Bank site: downloadlink.org

Solutions Manual for Logic and Computer Design Fundamentals 5th Edition by Mano IBSN 9780133760637. Solutions Manual for Logic and Computer Design Fundamentals 5th Edition by Mano IBSN 9780133760637 Author: Mano"