WIXLIB

defines eight 8-bit values: 01, 23, 45, 67, 89, AB, CD, EF. These values will be loadedconsecutively into the memory.The Sequential Read function is used to read the contents of the SDRAM and fill them into a file asfollows:1. Specify the hexadecimal starting address in the Address box.2. Specify the hexadecimal number of bytes to be copied into the file in the Length box. If theentire contents of the SDRAM are to be copied (which involves all 64 Mbytes), then place acheckmark in the Entire Memory box.3. Press Load Memory Content to a File button.4. When the Control Panel responds with the standard Windows dialog box asking for thedestination file, specify the desired file in the usual manner.2. 5 AccelerometerThe G-Sensor in the accelerometer utilizes a spirit level to function. The user can rotate theDE10-LIte board different directions, up or down, left or right. The bubble will travel quickly travelin respect to the user’s movements. Meanwhile, the control panel will show the accelerated data inx-axis, y-axis and z-axis as shown in Figure 2-7. Note that the resolution measurement of 3-axisesaccelerometer is set to /- 2g.Figure 2-7 Level by G-SensorDE10-LiteUser Manual14www.terasic.comNovember 21, 2016

2. 6 VGADE10-Lite Control Panel provides VGA pattern function that allows users to output color pattern toLCD/CRT monitor using the DE10-Lite board. Follow the steps below to generate the VGA patternfunction:Choosing the VGA tab leads you to the window in Figure 2-8.Plug a D-sub cable to the VGA connector of the DE10-Lite board and LCD /CRT monitor.The LCD/CRT monitor will display the same color pattern on the control panel window.Click the drop down menu shown in Figure 2-8 where you can output the selected patternindividually.Figure 2-8 Controlling VGA display under Control PanelDE10-LiteUser Manual15www.terasic.comNovember 21, 2016

2. 7 Overall Structure of the DE10-Lite Control PanelThe DE10-Lite Control Panel is based on a Nios II Qsys system instantiated in the MAX 10 FPGAwith software running on the on-chip memory. The software was implemented in coding LanguageC; and the hardware was implemented in Verilog HDL code with Qsys builder. The source code isnot available on the DE10-Lite System CD.To run the Control Panel, users should follow the configuration setting according to Section 3.1.Figure 2-9 depicts the structure of the Control Panel. Each input/output device is controlled by theNios II Processor instantiated in the FPGA chip. The communication with the PC is done via theUSB Blaster link. The Nios II interprets the commands sent from the PC and performs thecorresponding actions.Figure 2-9 The block diagram of the DE10-Lite control panelDE10-LiteUser Manual16www.terasic.comNovember 21, 2016

Chapter 3Using the Starter KitThis chapter provides instructions to use the board and describes the peripherals.3. 1 Configuration of MAX 10 FPGA on DE10-LiteThere are two types of configuration method supported by DE10-Lite:1. JTAG configuration: configuration using JTAG ports.JTAG configuration scheme allows you to directly configure the device core through JTAG pins TDI, TDO, TMS, and TCK pins. The Quartus II software automatically generates .sof files that areused for JTAG configuration with a download cable in the Quartus II software program.2. Internal configuration: configuration using internal flash.Before internal configuration, you need to program the configuration data into the configurationflash memory (CFM) which provides non-volatile storage for the bit stream. The information isretained within CFM even if the DE10-Lite board is turned off. When the board is powered on, theconfiguration data in the CFM is automatically loaded into the MAX 10 FPGA. JTAG Chain on DE10-Lite BoardThe FPGA device can be configured through JTAG interface on DE10-Lite board, but the JTAGchain must form a closed loop, which allows Quartus II programmer to the detect FPGA device.Figure 3-1 illustrates the JTAG chain on DE10-Lite boardFigure 3-1DE10-LiteUser ManualThe JTAG configuration scheme17www.terasic.comNovember 21, 2016

Configure the FPGA in JTAG ModeThe following shows how the FPGA is programmed in JTAG mode step by step.1.Open the Quartus II programmer, please Choose Tools Programmer. The Programmerwindow opens. See Figure 3-2.Figure 3-2 Programmer Window2.3.Click “Hardware Setup”, as circled in Figure 3-2.If it is not already turned on, turn on the USB-Blaster [USB-0] option under currently selectedhardware and click “Close” to close the window. See Figure 3-3.DE10-LiteUser Manual18www.terasic.comNovember 21, 2016

Figure 3-3 Hardware Setting4.Click “Auto Detect” to detect all the devices on the JTAG chain, as circled in Figure 3-4.Figure 3-4 Detect FPGA device in JTAG modeDE10-LiteUser Manual19www.terasic.comNovember 21, 2016

5.Select detected device associated with the board, as circled in Figure 3-5.xFigure 3-5 Select 10M50DA device6.FPGA is detected, as shown in Figure 3-6.Figure 3-6 FPGA detected in Quartus II programmerDE10-LiteUser Manual20www.terasic.comNovember 21, 2016

7.Right click on the FPGA device and click “Change File” to open the .sof file to beprogrammed, as highlighted in Figure 3-7.Figure 3-7 Open the .sof file to be programmed into the FPGA device8.Select the .sof file to be programmed, as shown in Figure 3-8.Figure 3-8 Select the .sof file to be programmed into the FPGA deviceDE10-LiteUser Manual21www.terasic.comNovember 21, 2016

9.Click “Program/Configure” check box and then click “Start” button to download the .sof fileinto the FPGA device, as shown in Figure 3-9.Figure 3-9 Program .sof file into the FPGA device Internal Configuration The configuration data to be written to CFM will be part of the programmer object file(.pof). This configuration data is automatically loaded from the CFM into the MAX 10devices when the board is powered up.Please refer to Chapter 8: Programming the Configuration Flash Memory (CFM) for thebasic programming instruction on the configuration flash memory (CFM).Figure 3-10 High-Level Overview of Internal Configuration for MAX 10 DevicesDE10-LiteUser Manual22www.terasic.comNovember 21, 2016

Status LEDThe DE10-Lite development board includes board-specific status LEDs to indicate board status.Please refer to Table 3-1 for the description of the LED indicator. Please refer to Figure 3-11 fordetailed LED location.Figure 3-11 Status LED positionTable 3-1 Status LEDReferenceLED NameDescriptionD1ULEDIlluminates when the on-board USB-Blaster is workingD2CONF DONEIlluminates when the FPGA is successfully configured.D35VIlluminates when Input power is active. Not Installed.D4Power GoodIlluminates when board power system is OK.DE10-LiteUser Manual23www.terasic.comNovember 21, 2016

3. 2 Clock Circuitr yFigure 3-12 shows the default frequency of all external clocks to the MAX 10 FPGA. A clockgenerator is used to distribute clock signals with low jitter. The two 50MHz clock signals connectedto the FPGA are used as clock sources for user logic. One 24MHz clock signal is connected to theclock inputs of USB microcontroller of USB Blaster. One 10MHz clock signal is connected to thePLL1 and PLL3 of FPGA, the outputs of these two PLLs can drive ADC clock. The associated pinassignment for clock inputs to FPGA I/O pins is listed in Table 3-2.Warning !!Do not modify the clock generator settings.Incorrect setting will cause the system to not work.Figure 3-12 Clock circuit of the FPGA BoardTable 3-2 Pin Assignment of Clock InputsSignal NameFPGA Pin No.DescriptionI/O StandardADC CLK 10PIN N510 MHz clock input for ADC (Bank 3B)3.3-V LVTTLMAX10 CLK1 50PIN P1150 MHz clock input(Bank 3B)3.3-V LVTTLMAX10 CLK2 50PIN N1450 MHz clock input(Bank 3B)3.3-V LVTTLDE10-LiteUser Manual24www.terasic.comNovember 21, 2016

3. 3 Using the Push-buttons, Switches and LEDs User-Defined Push-buttonsThe board includes two user defined push-buttons that allow users to interact with the MAX 10FPGA device as shown in Figure 3-13. MAX 10 FPGA devices support Schmitt trigger input on allI/O pins. A Schmitt trigger feature introduces hysteresis to the input signal for improved noiseimmunity, especially for signal with slow edge rate and act as switch debounce in Figure 3-14 forthe push-buttons connected. Table 3-3 list the pin assignment of user push-buttons.Figure 3-13 Connections between the push-button and MAX 10 FPGAPushbutton depressedPushbutton releasedBeforeDebouncingSchmitt TriggerDebouncedFigure 3-14Switch debouncingTable 3-3 Pin Assignment of Push-buttonsSignal NameFPGA Pin No.DescriptionI/O StandardKEY0PIN B8Push-button[0]3.3 V SCHMITT TRIGGER"KEY1PIN A7Push-button[1]3.3 V SCHMITT TRIGGER"DE10-LiteUser Manual25www.terasic.comNovember 21, 2016

User-Defined Slide SwitchThere are ten slide switches connected to FPGA on the board (See Figure 3-15). These switches areused as level-sensitive data inputs to a circuit. Each switch is connected directly and individually toa pin on the MAX 10 FPGA. When the switch is in the DOWN position (closest to the edge of theboard), it provides a low logic level to the FPGA, and when the switch is in the UP position itprovides a high logic level. Table 3-4 list the pin assignments of the user switches.Figure 3-15Connections between the slide switches and MAX 10 FPGATable 3-4 Pin Assignment of Slide SwitchesSignal NameFPGA Pin No.DescriptionI/O StandardSW0PIN C10Slide Switch[0]3.3-V LVTTLSW1PIN C11Slide Switch[1]3.3-V LVTTLSW2PIN D12Slide Switch[2]3.3-V LVTTLSW3PIN C12Slide Switch[3]3.3-V LVTTLSW4PIN A12Slide Switch[4]3.3-V LVTTLSW5PIN B12Slide Switch[5]3.3-V LVTTLSW6PIN A13Slide Switch[6]3.3-V LVTTLSW7PIN A14Slide Switch[7]3.3-V LVTTLSW8PIN B14Slide Switch[8]3.3-V LVTTLSW9PIN F15Slide Switch[9]3.3-V LVTTLDE10-LiteUser Manual26www.terasic.comNovember 21, 2016

User-Defined LEDsThere are also ten user-controllable LEDs connected to FPGA on the board. Each LED is drivendirectly and individually by a pin on the MAX 10 FPGA; driving its associated pin to a high logiclevel turns the LED on, and driving the pin low turns it off. Figure 3-16 shows the connectionsbetween LEDs and MAX 10 FPGA. Table 3-5 list the pin assignment of user LEDs.Figure 3-16Connections between the LEDs and MAX 10 FPGATable 3-5 Pin Assignment of LEDsSignal NameFPGA Pin No.DescriptionI/O StandardLEDR0PIN A8LED [0]3.3-V LVTTLLEDR1PIN A9LED [1]3.3-V LVTTLLEDR2PIN A10LED [2]3.3-V LVTTLLEDR3PIN B10LED [3]3.3-V LVTTLLEDR4PIN D13LED [4]3.3-V LVTTLLEDR5PIN C13LED [5]3.3-V LVTTLLEDR6PIN E14LED [6]3.3-V LVTTLLEDR7PIN D14LED [7]3.3-V LVTTLLEDR8PIN A11LED [8]3.3-V LVTTLLEDR9PIN B11LED [9]3.3-V LVTTLDE10-LiteUser Manual27www.terasic.comNovember 21, 2016

3. 4 Using the 7-segment DisplaysThe DE10-Lite board has six 7-segment displays. These displays are paired to display numbers invarious sizes. Figure 3-17 shows the connection of seven segments (common anode) to pins onMAX 10 FPGA. The segment can be turned on or off by applying a low logic level or high logiclevel from the FPGA, respectively.Each segment in a display is indexed from 0 to 6 and DP (decimal point), with correspondingpositions given in Figure 3-17. Table 3-6 shows the pin assi zgnment of FPGA to the 7-segmentdisplays.Figure 3-17 Connections between the 7-segment display HEX0 and the MAX 10 FPGATable 3-6 Pin Assignment of 7-segment DisplaysSignal NameFPGA Pin No.DescriptionI/O StandardHEX00PIN C14Seven Segment Digit 0[0]3.3-V LVTTLHEX01PIN E15Seven Segment Digit 0[1]3.3-V LVTTLHEX02PIN C15Seven Segment Digit 0[2]3.3-V LVTTLHEX03PIN C16Seven Segment Digit 0[3]3.3-V LVTTLHEX04PIN E16Seven Segment Digit 0[4]3.3-V LVTTLHEX05PIN D17Seven Segment Digit 0[5]3.3-V LVTTLHEX06PIN C17Seven Segment Digit 0[6]3.3-V LVTTLHEX07PIN D15Seven Segment Digit 0[7], DP3.3-V LVTTLHEX10PIN C18Seven Segment Digit 1[0]3.3-V LVTTLHEX11PIN D18Seven Segment Digit 1[1]3.3-V LVTTLHEX12PIN E18Seven Segment Digit 1[2]3.3-V LVTTLDE10-LiteUser Manual28www.terasic.comNovember 21, 2016

HEX13PIN B16Seven Segment Digit 1[3]3.3-V LVTTLHEX14PIN A17Seven Segment Digit 1[4]3.3-V LVTTLHEX15PIN A18Seven Segment Digit 1[5]3.3-V LVTTLHEX16PIN B17Seven Segment Digit 1[6]3.3-V LVTTLHEX17PIN A16Seven Segment Digit 1[7] , DP3.3-V LVTTLHEX20PIN B20Seven Segment Digit 2[0]3.3-V LVTTLHEX21PIN A20Seven Segment Digit 2[1]3.3-V LVTTLHEX22PIN B19Seven Segment Digit 2[2]3.3-V LVTTLHEX23PIN A21Seven Segment Digit 2[3]3.3-V LVTTLHEX24PIN B21Seven Segment Digit 2[4]3.3-V LVTTLHEX25PIN C22Seven Segment Digit 2[5]3.3-V LVTTLHEX26PIN B22Seven Segment Digit 2[6]3.3-V LVTTLHEX27PIN A19Seven Segment Digit 2[7] , DP3.3-V LVTTLHEX30PIN F21Seven Segment Digit 3[0]3.3-V LVTTLHEX31PIN E22Seven Segment Digit 3[1]3.3-V LVTTLHEX32PIN E21Seven Segment Digit 3[2]3.3-V LVTTLHEX33PIN C19Seven Segment Digit 3[3]3.3-V LVTTLHEX34PIN C20Seven Segment Digit 3[4]3.3-V LVTTLHEX35PIN D19Seven Segment Digit 3[5]3.3-V LVTTLHEX36PIN E17Seven Segment Digit 3[6]3.3-V LVTTLHEX37PIN D22Seven Segment Digit 3[7] , DP3.3-V LVTTLHEX40PIN F18Seven Segment Digit 4[0]3.3-V LVTTLHEX41PIN E20Seven Segment Digit 4[1]3.3-V LVTTLHEX42PIN E19Seven Segment Digit 4[2]3.3-V LVTTLHEX43PIN J18Seven Segment Digit 4[3]3.3-V LVTTLHEX44PIN H19Seven Segment Digit 4[4]3.3-V LVTTLHEX45PIN F19Seven Segment Digit 4[5]3.3-V LVTTLHEX46PIN F20Seven Segment Digit 4[6]3.3-V LVTTLHEX47PIN F17Seven Segment Digit 4[7] , DP3.3-V LVTTLHEX50PIN J20Seven Segment Digit 5[0]3.3-V LVTTLHEX51PIN K20Seven Segment Digit 5[1]3.3-V LVTTLHEX52PIN L18Seven Segment Digit 5[2]3.3-V LVTTLHEX53PIN N18Seven Segment Digit 5[3]3.3-V LVTTLHEX54PIN M20Seven Segment Digit 5[4]3.3-V LVTTLHEX55PIN N19Seven Segment Digit 5[5]3.3-V LVTTLHEX56PIN N20Seven Segment Digit 5[6]3.3-V LVTTLHEX57PIN L19Seven Segment Digit 5[7] , DP3.3-V LVTTLDE10-LiteUser Manual29www.terasic.comNovember 21, 2016

3. 5 Using 2x20 GPIO Expansion HeadersThe board has one 40-pin expansion headers. Each header has 36 user pins connected directly to theMAX 10 FPGA. It also comes with DC 5V (VCC5), DC 3.3V (VCC3P3), and two GND pins.Both 5V and 3.3V can provide a total of 5W power.Figure 3-18 shows the related schematics. Table 3-7 shows the pin assignment of GPIO headers.GPIO(JP1)PIN V10GPIO [0]12GPIO [1]PIN W10PIN V9GPIO [2]34GPIO [3]PIN W9PIN V8GPIO [4]56GPIO [5]PIN W8PIN V7GPIO [6]78GPIO [7]PIN W7PIN W6GPIO [8]910GPIO [9]PIN V55V1112GNDPIN W5GPIO [10]1314GPIO [11]PIN AA15PIN AA14GPIO [12]1516GPIO [13]PIN W13PIN W12GPIO [14]1718GPIO [15]PIN AB13PIN AB12GPIO [16]1920GPIO [17]PIN Y11PIN AB11GPIO [18]2122GPIO [19]PIN W11PIN AB10GPIO [20]2324

User Manual 6 November 21, 2016 www.terasic.com. Coonnne. eccttors. s 2x20 GPIO Header Arduino Uno R3 Connector, including six ADC channels. Dissp. pl. laayy 4-bit resistor-network DAC for VGA (With 15-pin high-density D-sub connector) Swwiit. tc. chheess,, aBBuuttttoonnss anndd LLEEDDss 10 LEDs 10 Slide Switches 2 Push Buttons with Debounced.