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Enabling An Interconnected Digital WorldCadence EDA and IP UpdateJonathan SmithDirector, Strategic AlliancesJune 1, 2017

IoT Market Definition and Growth EstimatesLarge and widely varyingKnown: “IoT” will include a large mixed-signal component,with complex packaging2 2017 Cadence Design Systems, Inc. All rights reserved.

Cadence Implementation LeadershipTechnology innovation: fast, smart, and optimizedImplementation FabricCommon Engines, UI, and FlowsGenus Modus FRONT ENDLogicalElectricalPPA EnginesPhysicalConformal Timing, PowerOptimizationQuantus and DRCInnovus PLACE and ROUTEQuantus Tempus Voltus Pegasus DESIGN RULE CHECKELECTRICAL SIGNOFFMassively parallel for speed and capacityBest PPA and intelligent flowsRapid convergence and ECOFully integrated mixed signal3 2017 Cadence Design Systems, Inc. All rights reserved. Best-in-class core tools Common foundationengines Differentiated productivity

Cadence Custom IC and PCB Design LeadershipEnabling smart product design from start to rate VarietyVirtuoso Spectre Allegro VirtuosoAllegro PSpice OrCAD Sigrity Market leadership forover 25 yearsMixed signalAnalog/RFAdvanced node (16nm to 5nm)Photonics supportDifferentiated andcomprehensivesupport for IoT,automotive, andaero/defense designsRigid-flex board enablementAdvanced packagingSystem Design Enablement via an Extensive Ecosystem4 2017 Cadence Design Systems, Inc. All rights reserved.In excess of 70 differentecosystem partners

Cadence Verification SuiteTechnology innovation leadership: fast, smart, and optimizedVerification FabricUniform multi-engine verificationVIPvManager Indago Perspec VERIFICATION IPMETRICSDEBUGSW-DRIVEN TESTJasperGold Xcelium Palladium Z1Protium S1FORMAL and STATICSIMULATIONEMULATIONFPGA PROTOTYPETotal throughputMetric-driven signoffApplication optimizedCloud-centric architecture5 2017 Cadence Design Systems, Inc. All rights reserved. Fast: Best-in-class engines Smart: Flow-driven engineintegrations Optimized:Comprehensive solutions

Successful Foundry Node Requires an EcosystemStrong collaboration history – tool enablement and design flows2015Digital andSignoff Tools22FDX enabled62016V0.5 22FDX tapeoutsupportedEAD in 22FDX at CDNLive 2017 Cadence Design Systems, Inc. All rights reserved.2017Phase III of 22FDX reference flowDigital reference flow for 28FDSpresented at CDNLiveVoltus 28FDS certificationpresented at CDNLive

Samsung-Cadence Collaboration on 28FDSOICadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process TechnologyReference flow enables system and semiconductor companies to accelerate delivery of IoT and mixed-signal designs on Samsung’s processSAN JOSE, Calif., May 24, 2017—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its custom/analog tools and fullflow digital and signoff tools have achieved certification for the process design kit (PDK) and foundation library for the SamsungElectronics’ 28nm fully depleted silicon-on-insulator (FDS), also known as FD-SOI , process technology. The Cadence 28nm FDSreference flow has been certified by Samsung using a quad-core design with the ARM Cortex -A53 processor covering forward bodybias (FBB) with a bias controller, a power-gating scheme, UPF2.1 compliance, multi-bit FF optimization, SCAN/PMBIST/ATPG andSI/EM-aware design.7 2017 Cadence Design Systems, Inc. All rights reserved.

SOI Advanced-Node EDA Enablement – 28FDSDesign Capabilities28FDSLogic Simulation (Incisive)Digital Implementation and Signoff(RTL to GDS)Synthesis (Genus)Samsung 28FDS Cadence Digital Reference Flow presented at CDNLive SiliconValley 2017: “ Fast Ramp to Reap 28FDSOI Benefits ”Power Analysis (Joules)Test (Modus)Place and Route (Innovus)Timing Analysis (Tempus)Extraction (Quantus)EM/IR Analysis (Voltus)Physical Verification (PVS)Litho Physical Analysis (DFM/LPA)Litho Electrical Analysis (DFM/LEA)Custom and AnalogDesignChemical Mechanical Polishing (DFM/CMP)Schematic Editing (Virtuoso VSE)Analog Design Environment (Virtuoso ADE)Layout System (Virtuoso VLS)Circuit Simulation (Spectre APS/XLS)Electrically Aware Design (EAD)EM/IR Analysis (Voltus-Fi)Certified8 2017 Cadence Design Systems, Inc. All rights reserved.Enabled

SOI Advanced-Node EDA Enablement – 22FDXDesign Capabilities22FDXLogic Simulation (Incisive)Digital Implementation and Signoff(RTL to GDS)Synthesis (Genus)Power Analysis (Joules)Test (Modus)Place and Route (Innovus)Timing Analysis (Tempus)Extraction (Quantus)EM/IR Analysis (Voltus)Physical Verification (PVS)Litho Physical Analysis (DFM/LPA)Litho Electrical Analysis (DFM/LEA)Custom and AnalogDesignChemical Mechanical Polishing (DFM/CMP)Schematic Editing (Virtuoso VSE)Analog Design Environment (Virtuoso ADE)Layout System (Virtuoso VLS)Circuit Simulation (Spectre APS/XLS)Electrically Aware Design (EAD)EM/IR Analysis (Voltus-Fi) 12FDX: Cadence and GLOBALFOUNDRIES havestarted collaborating to support 12FDX nodeCertified9 2017 Cadence Design Systems, Inc. All rights reserved.EnabledThis slide contains forward-looking statements about Cadence business or products . Actual results may differ materially from the information presented here.

Enabling FD-SOI ProcessGenus DesignExplorationReleased in December 2016Innovus Body-BiasInterpolationTo be Released by end of May2017Tempus Body-BiasInterpolationTo be Released by end of May2017Voltus Body-BiasInterpolationTo be Released by November201710 2017 Cadence Design Systems, Inc. All rights reserved.This slide contains forward-looking statements about Cadence business or products . Actual results may differ materially from the information presented here.

project setup.tclBlock Tim ing ModelBlock LEF*IEEE 1801Power IntentTechnologyFilesStd CellLibrariesTop-Level FlowBlock-Level FlowGenus Synthesis SolutionLogic SynthesisDFT Insertion*Conformal Low Power CheckerConformal Equivalence CheckerModusATPGDigital Implementation andIn-Design SignoffWrite Abstract LEF*AssembleDesignParasitic RC ExtractionExtract Tim ing ModelTiming and SISignoffTempus Timing Signoff Solution11 2017 Cadence Design Systems, Inc. All rights reserved.Power IntegrityEMIR SignoffBest-in-Class PPA Optimizationpost syn and post pnrLEC/LP CheckQuantus QRC Extraction SolutionRTL SDC DFTFilesModus Test SolutionInnovus Implementation SystemPhysical Verification SystemLitho Physical AnalyzerVoltus IC Power Integrity Solution

Cadence Tensilica Processor IPFor automotive applicationsISO 26262 Ready / ISO 9001 CertifiedMultiple rounds of experience delivering DIAs to automotive licenseesDigital radio and voice commandMulti-microphone voice command, and noise reductionMulti-channel audio decode andadvanced post-processing Shipping in volume; 12 HiFi licensees inautomotiveAcoustic noise cancellationDigital Radio receiver: HD Radio,DAB, DAB , DRM, T-DMBTensilica HiFi DSPsADAS vision processingEmbedded signal processingBattery managementRegenerative powermanagementEngine controlCabin environmental controlTensilica Fusion DSPsTelematics connectivity / RadarAdvanced Driver Assistance SystemsLane-departure warningTraffic signdetection /recognitionMultiple wins in nextgen ADAS systems12Fusion DSPs introduced2015, 2016, and 2017EmergencyServicesPeer-to-peer smart carnetworking for intelligentvehicle highway controlGPSFront-collision warningAutomatic high beamTensilica Vision DSPs 2017 Cadence Design Systems, Inc. All rights reserved.Built-in LTE Modem andWi-Fi Access PointTensilica ConnX DSPsRadar/Lidar Shipping in 1st V2V802.11p from NXP; Wins in future RadarADAS systems

Cadence Custom and Digital tools Ready for FD-SOI Multi-year collaboration with foundry FD-SOI leaders PDK enablement, tool readiness, design flows in place Enables designers to take optimal advantage of FD-SOI features such as bodybiasing13 2017 Cadence Design Systems, Inc. All rights reserved.

Thank You14 2017 Cadence Design Systems, Inc. All rights reserved.

2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks ofCadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Backup16 2017 Cadence Design Systems, Inc. All rights reserved.

GF 22FDSOI Digital Reference Flow OverviewThe CDNS-GF 22FDSOI Digital Reference Flow is a RTL2GDS2 solution includingSynthesis (Genus), Place and Route (Innovus), Parasitic Extraction (Quantus), StaticTiming Analysis (Tempus), Power Analysis (Voltus), Formal Verification (Conformal),Test Solution (Modus), Physical Verification (PVS) and DFM (MVS) tools. The flowcovers block-level flow and hierarchical multi-bias domain flow.The hierarchical reference flow (P5) uses a bias generator and a processor monitor togenerate bias voltage for three bias domains. The CPU, timer block and top-level logicare physically placed in three different domains separated by boundary cells. Globalphysical cell placement and bias power network routing are performed during floorplanning.The block-level reference flow (P2/P4) uses OR1200 RTL with Invecas Standard Cellsfor official digital reference flow release, with industry-standard CPU RTL is also used forPPA benchmark in P2. The reference flows include both all-in-one make file for RTL-toGDSII and standalone make file for each step.17 2017 Cadence Design Systems, Inc. All rights reserved.

Key Features at Phased Releases P2 first released on Aug 14, 2015 Basic digital reference flow including RC, Innovus, Quantus, Tempus Block level with only FBB cells, external back bias voltage Bias routing to WellTAP cell from external power pins, one BIAS voltage pair (NW, PW), withdifferent BIAS voltages P4 first released on Nov 6, 2015 1801 low-power flow with 3 power domains Genus, Conformal, Incisive, and ET are also added to P2 Implementation of Mixed Vt due to various bias conditions Bias routing to WellTAP cell from external power pins, multiple BIAS voltage pairs, with predefined voltage level per domain P5 first released on April 30, 2016 Bottom-up hierarchical low power flow with body bias IP to generate body bias voltage Bias routing to WellTAP cells, multiple BIAS voltage pairs, with different BIAS voltages fordifferent domains18 2017 Cadence Design Systems, Inc. All rights reserved.

2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks ofCadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Allegro PSpice OrCAD Mixed signal . Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS ProcessTechnology Reference flow enables system and semiconductor companies to accelerate delivery of IoT and mixed-signal designs on Samsung's process SAN JOSE, Calif., May 24, 2017—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its custom/analog .