WIXLIB

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013Packaging for theCloud Computing EraIlyas MohammedJanuary 24, 2013ContentsCloudComputingDIMM-in-aPackage/xFDBVA PoPConclusionsCli t SClient-ServerDesigng andPerformanceF tFeaturesR ryChallengesh llApplicationslReliabilityResultsxFD forDIMMs2www.cpmt.org/scv1

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology BVA PoPConclusionsCli t SClient-ServerDesigng andPerformanceF tFeaturesR ryChallengesh llApplicationslReliabilityResultsxFD forDIMMs3Client: Mobile Devices as Digital Alter Ego4www.cpmt.org/scv Mobile device is becoming the single one that does everything. This requires high computing performance and wireless data at low power in smallform factors.2

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013Wireless Network: Making Mobile Computing PossibleThe classic client-server model“The network is the computer”Wired networkFunctionally similar (difference largely in scale)Similar packaging (processors, memory, harddrives, etc.)The current cloud computing model“The internet at hand”Wireless networkFunctionally different (phones, tablets,laptops, servers)Different packaging (integrated vs. discrete) High wireless bandwidth allows for full functionality and mobility5Impact on PackagingDesktop computingPluggable componentsUpgradeableStandards drivenMobile computingIntegrated componentsNon-upgradeableClosed (vertically integrated) The trend towards integrated and closed systemshas performance and design benefits. This has tremendous impact on packaging including3D chip packagingModules and interposerso Passives integrationo Connectors and socketsoo6www.cpmt.org/scv3

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013The Critical InterconnectProcessing and access timesData size & access hierarchy CPU-memory gap: it takes far longer to get data to the processor than it takes to use it Processor-memory interface is the most critical one for computing performance7Processor-Memory Architecture The interconnect determines the computing performance and power usage8www.cpmt.org/scv4

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology BVA PoPConclusionsCli t SClient-ServerDesigng andPerformanceF tFeaturesR ryChallengesh llApplicationslReliabilityResultsxFD forDIMMs9Miniaturization of a DIMM to a PackageSO-DIMMDIMM-in-a-PackageSO-DIMM67.6mm x 30mm x 3.8mmDIMM-in-a-Package22.5mm x 17.5mm x 1.2mm204 pins at 0.6 mm pitch407 BGA at 0.8mm x 0.8mm pitchLower performance than a singlepackage due to boards andconnectorsSame high performance as a singlepackage due to BGA directly tomotherboardAdvantage81% area reduction94% volume reductionTwice the pins for betterpower/ground and IO optionsDDR4/DDR5Higher reliability DIMM-in-a-Package is ideal for high performing mobile platforms10www.cpmt.org/scv5

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013FeaturesWithout moldWithout moldBottom viewSide view (without mold)Top viewFront view (without mold) Functionally equivalent to a standard DIMM 4 chips in a single package (more chips possible) Face-down wire-bond through windows for high performance11Specifications Quad-chip Face-Down Wire-bondBGA Package 407 BGA at 0.8mm x 0.8mm pitch 22.5mm x 17.5mm x 1.2mm packagesize Standard wire-bond CSP process Single-step overmold including thewindows Pb-free 0.45mm solder ball diameter12www.cpmt.org/scv6

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013AssemblyWire-bondChip attachMold and BGA attach The first layer of chips areattached, then a second layerof chips are attached (with aspacer if necessary), wirebonded through the windows,molded, BGA attached andthen marked and singulated.13Functional BGA LayoutA1 Corner 1A1AcornerB VSSC DQ5D NCE DQ3F ResetG VDDH VDDJNCK NCL VrefCAM VSSN ZQP VDDR VDDT DQ8U VSSV NCW DQ14Y 12VDDQ678910111213151617181920212223242526A0 i2c VDD i2c DQ54VSSDQ7VDDVDDVDDZQNC VrefDQ NCVDDVDDVDDVSSDQ15VSSDQ13VSSVDDQNCVSSEventb VDDQ VSS Reset DQSL DQ3SCL DQ4 DQ6 VSS DQSLB VSSSDA VDDQ VDDQ VSS VSS VSSVSSDQ2VSSDQ0DQ1NCDML VrefCA DMHVSS VSS VSSNC NC NCDQ8DQ9NCVSS DQ11 DQSH VSSDQ10 VSS DQSHB VSSVSS VSS VSS VSSA1 i2cA2 2VSSDQ135A9 VDD A8BA0 A6 A7A12 VSSCA A14NC CLK CLKBCKE0 VSSCA BA2A10 A5 CKE1ODT0 VDD A15VDDQ VDDQ VSS VSS VSSVDDQ DQ15 VSS DQSHB VSSDQ14 VSS VSS DQSH VDDVSS VSS DQ10 VSS DQ8VSSVSSDQ9VDD14A1 A13 A11 VDD A11 A13VDD A0 CS1 NC CS3 A0BA1 A2 A4 NC A4 A2NC NC A3 VSSCA A3 CLKBCAS VSSCA RAS NC RAS VSSCAVDD WE ODT1 NC ODT3 WENC NC CS0 VDD CS2 SSResetVSSDQ3VSSVDDVSSVSSDQ1VDDNCVSSVSSZQNC NCDMH VSSVSS VrefCANC VrefDQNCDMLVSSNCNCVSSVSSVSSVSS VSS VDDQ VDDQ VSS DQ12DQ14 DQ12 VDDQ VDDQ DQ15 VSSVSS VDDQ VDDQ VDDQ VDDQ DQ14VSS VSS VSSVSS DQSHB DQSHVDD VSS VSSVDD A9VDD DQ9 DQ8A6 BA0VDD VSS DQ10VSSCA A12NC VDD DMHNC NCNC VSSCA VrefDQVSSCA NCNC VDD VSSA5 A10VDD VSS DMLVDD ODT2VDD DQ2 VSSVDD VSS DQ1VSS DQ3 VSSVDDQ DQSLB DQSLVSS VSS VSS VDDQ VDDQ VDDQ VDDQ DQ5VSS DQSLB VSS DQ7 VDDQ DQ4 VSS VDDQVDD DQSL VSS VSS DQ6 VDDQ DQ4 DQ7DQ0 VSS DQ2 VSS VSS DQ5 NC DDDQ0VSSNCDQ6VSS X64 data with two copies of address Distributed power and ground design A universal footprint supporting 2-8 DRAM devices of DDR, LPDDR and GDDR types14www.cpmt.org/scv7

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013Impact on PCB RoutingLow-profile laptop memory layoutDRAM routingDIMM-in-a-package routing Routing individual memory devices requires HDI PCB DIMM-in-a-Package has been specifically designed, including mirrored footprint forease of routing when mounted on either side of the PCB. This allows for routing on anon-HDI PCB, reducing system costs significantly15Ultrabook Implementation16www.cpmt.org/scv DIMM-in-a-Package successfully integrated within an ultrabook (the board was takenout to display the memory) Highest performance (even more than DRAM packages on PCB) at lowest cost(significant board cost savings)8

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013Server Side Memory Challenge: Low Power DensificationSource: EPA report, 2007 Datacenters consume more than 120 GWh(( 3%3% of total national electricity use) Memory is the biggest energy consumingcomponent Densification with high performance wouldsignificantly reduce power usage throughlower losses and lower voltage, and moreefficient thermal management17xFD Technology: High Performance Memory DensificationConventional approaches xFD offers face-down wire-bond interconnect for high performance for all the chipsin the package (2, 3, or 4 are possible) Conventional solutions suffer from asymmetric and low performance, besides beinghigher cost.18www.cpmt.org/scv9

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013High Performance in a Dense PackageData Eye Shmoo Plots at 2133 MT/s (15 unit sample size)Bottom chipTop chipSpeed Bin YieldDQDQS/DQS#BottomchipTopchipFace-upstack Equal high performance from both top and bottom chips (95 0C, Advantest 5501) There is 60% yield improvement at highest speed level compared to face-up stack There is also a 25% reduction in chip junction temperature compared to face-up stack19DIMM Boards: High Performance with Easy RoutingControl/Address routing of quad-rank 16 GB LRDIMM using single layer onlyModule TestedDescriptionOne DIMM (4 DQ loads)Two DIMMs (8 DQ loads)Invensas 8GBQuad-rank RDIMM72 1Gb (x4) 1333MHz chips(36 DFD packages) 1600MT/s1600MT/s (with tuning)1333MT/s (no tuning)Market 8GB Quadrank RDIMM36 2Gb (x8) 1333MHz chips(36 1-chip packages) 1600MT/s800MT/s (barely operates)20www.cpmt.org/scv 2-chip xFD (DFD) solution easily beats even single chip solution10

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology BVA PoPConclusionsCli t SClient-ServerDesigng andPerformanceF tFeaturesR ryChallengesh llApplicationslReliabilityResultsxFD forDIMMs21Ultra High IO Between Processor and MemoryBGA PoPTMV PoP2012 2013 2014IO Ultra-high IO interconnect technologyis needed to achieve the highbandwidth desired between theCPU/GPU and memory64642015256512DDR data-rate(Mb )(Mbps)Bandwidth (GB/s)800 16008008006.412.825.651.2PowerLow HighLowLowSource: Samsung22www.cpmt.org/scv11

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013BVA PoP: FeaturesTop ViewMemory-Logic InterfaceSide ViewBond Via Array (BVA) Stand-off issue eliminated: Wire-bondbased memory-logic interconnect 1000 wide IO: 0.2 mm pitch easily possible High performance at low-cost:Conventional PoP materials and processes23BVA PoP: Wide IO Support without TSV20102011Mobile Wide IOWide IOPackagingPoPPoPPoPPoPBVA PoPTSVMobile processor tomemoryinterconnect168168240240IO rangingg g from 200to 1000 1250Clock Speed(MHz)400533800Power2X1X0.8X# of alHigh IO offers highbandwidth at lowspeedEnables intermediatepower reductionsQuad Quad 12.8 12.8 12.82000.5X The goal of BVA PoP is to offer TSV capabilities for PoP applications utilizingconventional PoP infrastructure and materials.24www.cpmt.org/scv12

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013BVA PoP: Specifications 0.5 mmVery Fine Pitch Wire-Bond Interconnect 1 mmAssumptions: Package size: 14 mm x 14 mmIO edge to package edge: 0.5 mmIO area width: 1 mmPitch (mmm)No. of IO 600756456640784 960992 1220 1440 Assigning the same amount of area for IO as that of the current 0.5 mmpitch PoP, BVA with 0.2 mm pitch can offer up to 1440 IO.25BVA PoP ChallengesHow to form free-standing wire-bonds whoseend points are within tolerance (Δx, Δy, Δz)? There are 3 unique features that needto be demonstrated throughassembly and testing. Development engineering effort wascarried out to determine thefeasibility of this technology.How to expose the ends of the wire-bonds cleanlywithin a given height over mold surface?How to reliably join the top and bottom packagesat fine pitch with wire-bonds tips and solder?26www.cpmt.org/scv13

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013Test Vehicle DesignPackage size14 mm x 14 mmPackage thickness1.36 mmBottom IO pitch0.3 mm x 0.3 mmTop IO pitch0.24 mm x 0.24 mmNumber of IO rows2Number of top IO432 A 432 memory-logic interconnectswere designed at 0.24 mm x 0.24mm pitch to evaluate the feasibilityof BVA technology.27BVA PoP Process Flow The 3 process steps unique to BVA PoP are highlighted and will be discussed in detail.28www.cpmt.org/scv14

IEEE Santa Clara Valley Chapter, Components, Packagingand Manufacturing Technology Society1/24/2013Test Vehicle Assembly: Bottom Package The flip-chip package is shown in stripform after wire-bonding BVA) and beforeovermolding. The nominal height of the wire-bonds is0.52 mm.29Test Vehicle Assembly: PoP StackTop surface of bottom packageFully Assembled BVA PoP Package The top surface of the of the bottom package has bond wires projecting outwards byabout 0.1 mm. The two packages were joined using conventional PoP SMT approach.30www.cpmt.org/scv15