WIXLIB

Failing to Fail: Achieving Success inAdvanced Low Power Design using UPF1RickKoster, 2John Redmond,and 3Shreedhar Ramachandra1MentorGraphics Corporation2Broadcom Corporation3Synopsys Inc.International Symposium on Low Power Electronics and Design

UPF OverviewRick KosterMentor GraphicsInternational Symposium on Low Power Electronics and Design

Agenda UPF Overview– Low Power Management Concepts– What is UPF– Power Management Structures– Power Management Behavior3

Power Management Concepts Power Gating:– Shutting off power to portions of the design (PowerDomains) to eliminate leakage power consumption Multi Voltage Designs:– Organizing the design into different voltage domainsas a function of performance to minimize dynamicand static power consumption Voltage and Frequency Scaling– Dynamically tune parts of the design to meetperformance goals with minimum power Power Management requirements– Isolation, Level Shifting, State Retention, Switching4

What is UPF? An Evolving Standard––––Accellera UPF in 2007 (1.0)IEEE 1801-2009 UPF (2.0)IEEE 1801-2013 UPF (2.1)IEEE 1801A-2014 UPF (2.2) For Power Intent Based upon TCL– Tcl syntax and semantics– Can be mixed withnon-UPF TCL And HDLs– SystemVerilog, Verilog, VHDL– To define power For Verificationmanagement– Simulation or Emulation– To minimize power– Static/Formal Verificationconsumption And for Implementation– Through control of leakage– Synthesis, DFT, P&R, etc.5

Power Management Structures Power DomainsDomain Interfaces (ISO/LS)RetentionSupply SetsSupply Ports/NetsPower Switches6

Power Domains A collection of instances that are treated as agroup for power-management purposes. A Power domain exists within a logical scope– UPF and HDL identifiers must be unique within thescope– All UPF commands are executed within the currentactive scope A power domain can have associated with itisolation strategies, retention strategies andlevel shifter requirements7

Power Domainscreate power domain DUT PD –include scopecreate power domain C1 PD -elements {CPU1}create power domain C2 PD -elements {IP1 CPU2}C2 PDDUTC1 PDIP1CPU 2CPU1MemorycacheBUS/FabricP1P2P3IP2Power CTRLDUT PD8

Supply Sets Represent a collection of supply netsthat provide a power source.Supply NetsSupply Set– Consists of a set of up to 6 ldeeppwellMain power, ground, nwell, pwell, deepnwell,deeppwell– One supply net per (required) function– Electrically complete model of a powerdistribution network in a domain:Functionscreate power domain PD u1 –include scopecreate power domain PD u11 – elements {U1/U11}create power domain PD u12 –elements {U1/U12}power, ground, etc. Power domains have a few predefinedsupply sets: primary, default isolation,PRU1and default retention Supply sets can be associated withone another to model supplyconnections abstractlyIPIRPU11L1L2IRU12L3L4L59

Domain Interfaces Power gating can cause electrical and logicalproblems to adjacent domains.– Isolation is used to prevent these problems.– Isolation cell: An instance that passes logic values duringnormal mode operation and clamps its output to some specifiedlogic value when a control signal is asserted. Multi voltage designs can also experienceproblems– Level shifters are used to maintain signal integrity. Level shifter cell: An instance that translates signal values froman input voltage swing to a different output voltage swing.10

Retention/Repeaters Device operation may require the use of flipflops or memories that preserve state during adomain’s power down. Preserving state is achieve through the use ofUPF retention.– Retention: Enhanced functionality associated withselected sequential elements or a memory such thatmemory values can be preserved during the powerdown state of the primary supplies.11

Supply Ports/Nets Power Domain supply sets consist of supplynets that eventually are driven by supply ports Supply ports and nets are defined as objects ofsupply net type UPF package defines supply net type as:typedef enum(OFF 0,UNDETERMINED, PARTIAL ON, FULL ON) statetypedef struct packed {state state;int voltage; // voltage in microVolts} supply net type;12

Power Switches A power switch is a design element thatconditionally connects input supply nets to anoutput supply net A UPF switch can be on or off or partially on The state of the switch is set by Booleanfunctions of the control ports Match input voltage propagates to output (on) No Match output port disabled (off) Either power or ground can be switched13

set design top U1create power domain PD u1 –include scopecreate power domain PD u11 –elements {U1/U11}create power domain PD u12 –elements {U1/U12}create supply net sw1 out netcreate power switch SW1 \-domain PD u1 \-output supply port {swout sw1 out net} \-input supply port {swin PD u1.primary.power} \-control port {swctrl swCtl1} \-on state {SWon swin swctrl} \-off state {SWoff !swctrl}create supply set sw1 ss \-function {power sw1 out net} \-function {ground PD u1.primary.ground}associate supply set sw1 ss-handle PD u11.primaryassociate supply set PD u1.primary \-handle PD u11.default retentionassociate supply set PD u1.primary \-handle PD u11.default isolationset isolation iso pd u11 –domain PD u11 \-location self –clamp value {1} \-applies to outputsset retention ret pd u11 –domain PD u11 \-elements {U11/ret1} \-save signal {U11/ret n} high \-restore signal {U11/ret n low}UPF StructureCommand examplePIRIPRU1SW1RPIISOU12U11RET1L2L3L4RET514

create supply net sw2 out netcreate power switch SW2 \-domain PD u2 \-output supply port {swout sw2 out net} \-input supply port {swin PD u1.primary.power} \-control port {swctrl swCtl2} \-on state {SWon swin swctrl} \-off state {SWoff !swctrl}create supply set sw2 ss \-function {power sw2 out net} \-function {ground PD u1.primary.ground}associate supply set sw2 ss-handle PD u12.primaryassociate supply set PD u1.primary \-handle PD u12.default retentionassociate supply set PD u1.primary \-handle PD u12.default isolationset isolation iso pd u12 –domain PD u11 \-location self –clamp value {0} \-applies to outputsset retention ret pd u12 –domain PD u11 \-elements {U12/ret1} \-save signal {U12/ret n posedge}-restore signal {U12/ret n negedge}UPF StructureCommand 15

Behavior Supply set Power States Simstates Power Domain States16

Supply Sets Power States The power states of a supply set describe theexpected combination of states of the supplynets in the supply set– The state can be defined by a logic expression andmay include supply expression– State holds when logic expression is TRUE– A power state defines the legal values of supply setfunctions when in that state– Also may include a simstateadd power state PdA.primary-state GO MODE {–logic expr {SW ON } –simstate NORMAL-supply expr {{power {FULL ON 0.8}}&& {ground {FULL ON, 0}} && {nwell {FULL ON 0.8}}}-state OFF MODE {–logic expr {!SW ON} –simstate CORRUPT}-supply expr {power {OFF}}17

Simstates Simstate defines precise simulation semantics in thisstate. That is, the expected behavior of the cellsconnected to this supply set. CORRUPT– Combinational outputs corrupted– Sequential state/outputs corrupted CORRUPT ON ACTIVITY– Combinational outputs maintainedas long as inputs are stable– Sequential state/outputs corrupted CORRUPT ON CHANGE– Combinational outputs maintainedas long as outputs are stable– Sequential state/outputs corrupted NORMAL– Combinational logic functions normally– Sequential logic functions normally– Both operate with characterized timing CORRUPT STATE ON ACTIVITY– Combinational logic functions normally– Sequential state/outputs maintained aslong as inputs are stable CORRUPT STATE ON CHANGE– Combinational logic functions normally– Sequential state/outputs maintained aslong as outputs are stable18

Power States of a Power Domain A power domain is designed to have a set ofallowable states in which it can operate. The domain power states describe theallowable set of states for a domain. Eachstate is defined by a logic expression– Logic expressions can be created with: States of supply setsLogic port and net valuesSubdomain power statesInterval Functions19

Attributes Characteristics of a port or design element Used to identify power supplies for ports– set port attributes -ports Out1 -attribute \{UPF related power port “VDD”} Used to specify constraints for IP usage:– set port attributes –ports {logic port} –attribute \{UPF clamp value “1”} Used to specify structure and behavior– set design attributes –elements ALU1 –attribute \{UPF is leaf TRUE}– set design attributes –elements ALU1 –attribute \{UPF retention required}20

Summary UPF captures power intent of a design– Power gating, multiple voltage, dynamic voltage andfrequency scaling, isolation, retention, level shifting UPF works with HDL– Verilog, VHDL and SystemVerilog UPF guides verification and implementation UPF is an evolving standard––––Accellera UPF in 2007 (1.0)IEEE 1801-2009 UPF (2.0)IEEE 1801-2013 UPF (2.1)IEEE 1801a-2014 UPF (2.2)21

UPF For ASIC DesignJohn Redmond *Broadcom Corporation* Slides contributed by Sushma Honnavara-PrasadInternational Symposium on Low Power Electronics and Design

Agenda Introduction– How power intent is realized in silicon– Leaf Cells and macro models Soft IP modeling– Successive refinement– Constraints, configuration, implementation SoC integration– Hierarchical UPF composition– Supply network construction– System power states and transitions23

Introduction Power intent is captured through UPF, HDL and Library UPF realizes:– Supply network specification power/ground/nwell/pwell/deepnwell/deeppwell Macro and IO power connectivity On-chip power switch specification– Power domain specification Identify a standard cell region, supply availability in a region– Strategies and their implementation Dictates inference of isolation cells, level shifters, repeaters and retention cells Leaf cell/macros need models to identify supply pins– Liberty (.lib) provides UPF attributes– LEF identifies power/ground/signal pins– 1801-2013 enables cell and macro modeling24

Leaf Cells An instance that has no descendants orhas UPF is leaf cell attribute on it Typically refer to standard cells––––HDL – simulation modelUPF – low power cells specificationLiberty – implementationLEF – physical design Attributes of interest–––––supply vs signal pinssupply propertiescell attributespin attributesfunction attributes UPF specifies either explicit, implicit orautomatic supply connectivity to leaf cellstop modulesub modulesubmodulesub moduleleafcell (INVX1) {.pg pin (VDD) {.pg pin (VSS) {.25

Macros Also called IPs, a piece offunctionality optimized forpower/area/performance– Soft macros – handed off assynthesizable HDL (technologyagnostic)– Hard macros – handed off asLEF/GDS (technology specific) Also a leaf cell UPF is macro cell attribute allowsthe model to be recognized as partof lower boundary of the domaincontaining the instance Can be modeled as:Example of a hard macro –Embedded SRAM– UPF Power Models– Liberty models26

IP Modeling UPF Power models– Regular UPF commands enclosed betweenbeing power model and end power model– Applied on an IP instance using apply power model command– Models power states, port attributes, isolation etc. Liberty models– Pin, supply and cell based attributes available– switch pin, pg pin, is macro cell etc. Verilog simulation models– Model supply as logic functions27

Successive Refinement IP provider IP Source IP licensee Integrator Technologyspecificimplementation28