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SystemVerilog AssertionsVerificationIonuț Ciocîrlan Accellera Systems InitiativeAndra Radu1

Tutorial topics Introduction to SystemVerilog Assertions (SVAs) Planning SVA development Implementation SVA verification using SVAUnit SVA test patterns Accellera Systems Initiative2

Introduction to SystemVerilogAssertions(SVAs) Accellera Systems Initiative3

Assertions and properties What is an assertion?assert property (a - b)else error("Assertion failed!") What is a property?property p example;a - bendproperty Accellera Systems Initiative4

Simple assertion exampleproperty req to rise p;@(posedge clk) rose(req) - ##[1:3] rose(ack);endpropertyASSERT LABEL: assert property (req to rise p)else uvm error(“ERR", "Assertion failed") Accellera Systems Initiative5

Types of SystemVerilog Assertions Immediateassert (expression) pass statement[else fail statement] Concurrent Accellera Systems Initiative6

Assertions are used In a verification component In a formal proof kit In RTL generation“Revisiting Regular Expressions in SyntHorus2: from PSL SEREs to Hardware”(Fatemeh (Negin) Javaheri, Katell Morin-Allory, Dominique Borrione) For test patterns generation“Towards a Toolchain for Assertion-Driven Test Sequence Generation” (LaurencePIERRE) Accellera Systems Initiative7

SVAs advantages Fast Non-instrusive Flexible Coverable Accellera Systems Initiative8

Planning SVA development Accellera Systems Initiative9

Identify design characteristics Defined in a document (design specification) Known or specified by the designer The most common format is of the form cause andeffect: antecedent - consequent Antecedent: rose(req) Consequent: ##[1:3] rose(ack) Accellera Systems Initiative10

Keep it simple. Partition! Complex assertions are typically constructed fromcomplex sequences and properties.a ##1 b[*1:2] c ##1 d[*1:2] fell(a)sequence seq(arg1, arg2);arg1 ##1 arg2[*1:2];endsequenceseq(a, b) seq(c, d) fell(a) Accellera Systems Initiative11

Implementation Accellera Systems Initiative12

Coding guidelines Avoid duplicating design logic in assertions Avoid infinite assertions Reset considerations Mind the sampling clock Accellera Systems Initiative13

Coding guidelines (contd.) Always check for unknown condition (‘X’) Assertion naming Detailed assertion messages Assertion encapsulation Accellera Systems Initiative14

Best practices Review the SVA with the designer to avoid DSmisinterpretation Use strong in assertions that may never complete:assert property ( req - strong(##[1: ] ack)); Properties should not hold under certain conditions(reset, enable switch)assert property (@(posedge clk) disable iff (!setup reset)req - strong(##[1:3] ack)); Accellera Systems Initiative15

Best practices (contd.) Use the sampled() function in action blocksPrevious timeslotPreponedActiveInactiveNBAObservedassert property ( @(posedge clk) ack 0 )else begin uvm error("ERROR", sformatf("Assertion failed.ack is %d", t timeslot Accellera Systems Initiative16

Assertion example AMBA APB protocol specification:The bus only remains in the SETUP state for one clock cycleand always moves to the ACCESS state on the next rising edgeof the clock. Accellera Systems Initiative17

Assertion example (contd.) Antecedent (the SETUP phase)sequence setup phase s; rose(psel) and rose(pwrite)and (!penable) and (!pready);endsequence Consequent (the ACCESS phase)sequence access phase s; rose(penable) and rose(pready) and stable(pwrite) and stable(pwdata)and stable(paddr) and stable(psel);endsequence Accellera Systems Initiative18

Assertion example (contd.) The property can be expressed as:property access to setup p;@(posedge clk) disable iff (reset)setup phase s access phase s;endproperty The assertion will look like:assert property (access to setup p)else uvm error("ERR", "Assertion failed") Accellera Systems Initiative19

Does it work as intended? Accellera Systems Initiative20

SVA Verification with SVAUnit Accellera Systems Initiative21

SVA Verification ChallengesEasy to:- Update- Enhance- DisableClear separation betweenvalidation and SVA definitioncodePredictableResults should be:- Deterministic- Repeatable Accellera Systems Initiative22

Introducing SVAUnit Structured framework for Unit Testing for SVAs Allows the user to decouple the SVA definition from itsvalidation code UVM compliant package written in SystemVerilog Encapsulate each SVA testing scenario inside an unit test Easily controlled and supervised using a simple API Accellera Systems Initiative23

SVAUnit InfrastructureSVAUnit TestbenchSVAUnit Test SuiteSVAUnit TestSVAUnit Unit TestSVAUnit TestSVA interface containingSVASVAtest()ReportsReportsReportsReports Accellera Systems Initiative -24SVAUnit TestbenchEnables SVAUnitInstantiates SVAinterfaceStarts test -SVAUnit TestContains the SVAscenario -SVAUnit Test SuiteTest and test suitecontainer

Example specification AMBA APB protocol specification:The bus only remains in the SETUP state for one clock cycleand always moves to the ACCESS state on the next rising edgeof the clock. Accellera Systems Initiative25

Example APB interfaceinterface apb if (input dy;logic [ ADDR WIDTH-1 :0] paddr;logic [ WDATA WIDTH-1:0] pwdata;APB sequences definitionsAPB property definitionAPB assertion definitionendinterface Accellera Systems Initiative26

APB sequences definitions Antecedent (the SETUP phase)sequence setup phase s; rose(psel) and rose(pwrite)and (!penable) and (!pready);endsequence Consequent (the ACCESS phase)sequence access phase s; rose(penable) and rose(pready) and stable(pwrite) and stable(pwdata)and stable(paddr) and stable(psel);endsequence Accellera Systems Initiative27

APB property & assertiondefinitions The property can be expressed as:property access to setup p;@(posedge clk) disable iff (reset)setup phase s access phase s;endproperty The assertion will look like:assert property (access to setup p)else uvm error("ERR", "Assertion failed") Accellera Systems Initiative28

Example of SVAUnit Testbenchmodule top;// Instantiate the SVAUnit framework SVAUNIT UTILS.// APB interface with the SVA we want to testapb if an apb if(.clk(clock));initial begin// Register interface with the uvm config dbuvm config db#(virtual an if)::set(uvm root::get(), "*", “VIF", an apb if);// Start the scenariosrun test();end.endmodule Accellera Systems Initiative29

Example of SVAUnit Testclass ut1 extends svaunit test;// The virtual interface used to drive the signalsvirtual apb if apb vif;function void build phase(input uvm phase phase);// Retrieve the interface handle from the uvm config dbif (!uvm config db#(virtual an if)::get(this, "", “VIF", apb vif)) uvm fatal(“UT1 NO VIF ERR", "SVA interface is not set!")// Test will run by default;disable test();endfunctiontask test();// Initialize signals// Create scenarios for SVA verificationendtaskendclass Accellera Systems Initiative30

APB – SVAUnit test stepsEnable the APB SVAInitialize the interface signalsGenerate APB setup phase stimuliGenerate APB access phase stimuliSVA checks based on generated stimuli Accellera Systems Initiative31

Enable SVA and initialize signals.// Enable the APB SVAvpiw.disable all assertions();vpiw.enable assertion("APB PHASES");// Initialize signalstask initialize signals();apb vif.addr 32'b0;apb vif.wdata 32'b0;apb vif.write 1'b0;apb vif.enable 1'b0;apb vif.sel 1'b0;endtask. Accellera Systems Initiative32

Generate APB setup phase stimuli.task generate setup phase stimuli(bit valid);.// Stimuli for valid SVA scenariovalid 1 - write 1 && sel 1 && enable 0 && ready 0;// Stimuli for invalid SVA scenariovalid 0 - write ! 1 sel ! 1 enable ! 0 ready ! 0;.endtask. Accellera Systems Initiative33

Generate APB access phase stimuli.task generate access phase stimuli(bit valid);.// Constrained stimuli for valid SVA scenariovalid 1 - wdata apb vif.wdata && addr apb vif.addr &&write 1 && sel 1 && enable 1 && ready 1;// Constrained stimuli for invalid SVA scenariovalid 0 - wdata ! apb vif.wdata addr ! apb vif.addr write ! 1 sel ! 1 enable ! 1 ready ! 1;.endtask. Accellera Systems Initiative34

SVA state checking.if (valid setup phase)if (valid access phase)vpiw.fail if sva not succeeded("APB PHASES","The assertion should have succeeded!");elsevpiw.fail if sva succeeded("APB PHASES","The assertion should have failed!");elsevpiw.pass if sva not started("APB PHASES","The assertion should not have started!");. Accellera Systems Initiative35

Example of SVAUnit Test Suiteclass uts extends svaunit test suite;// Instantiate the SVAUnit testsut1 ut1;.ut10 ut10;function void build phase(input uvm phase phase);// Create the tests using UVM factoryut1 ut1::type id::create("ut1", this);.ut10 ut10::type id::create("ut10", this);// Register tests in suite add test(ut1);. add test(ut10);endfunctionendclass Accellera Systems Initiative36

SVAUnit Test APICONTROLCHECKREPORT disable all assertions(); enable assertion(sva name); enable all assertions();. fail if sva does not exists(sva name, error msg); pass if sva not succeeded(sva name, error msg); pass/fail if(expression, error msg);. print status(); print sva(); print report();. Accellera Systems Initiative37

SVAUnit FlowCreate SVAUnit TestbenchCreate an SVAUnit Test SuiteCreate an SVAUnit TestInstantiate test in Test SuiteImplement test() taskRegister tests in test suite Accellera Systems Initiative38SimulateScan report

Error reportingName of SVAUnitcheckSVAUnit test pathName of SVA undertest Accellera Systems InitiativeCustom errormessage39

Hierarchy report Accellera Systems Initiative40

Test scenarios exercised Accellera Systems Initiative41

SVAs and checks exercised Accellera Systems Initiative42

SVA test patterns Accellera Systems Initiative43

Simple implication test a and b crepeat (test loop count) beginrandomize(stimuli for a, stimuli for b, stimuli for c);interface.a stimuli for a;interface.b stimuli for b;@(posedge an vif.clk);interface.c stimuli for c;@(posedge interface.clk);@(posedge interface.clk);if (stimuli for a 1 && stimuli for b 1)if (stimuli for c 1)vpiw.fail if sva not succeeded("IMPLICATION ASSERT","The assertion should have succeeded!");elsevpiw.fail if sva succeeded("IMPLICATION ASSERT","The assertion should have failed!");elsevpiw.pass if sva not started("IMPLICATION ASSERT","The assertion should not have started!");end Accellera Systems Initiative44

Multi-threadantecedent/consequent a ##[1:4] b - ##[1:3] crepeat (test loop count) begin// Generate valid delays for asserting b and c signalsrandomize(delay for b inside {[1:4]}, delay for c inside {[1:3]});interface.a 1;repeat (delay for b)@(posedge interface.clk);interface.b 1;vpiw.pass if sva started but not finished("MULTITHREAD ASSERT","The assertion should have started but not finished!");repeat (delay for c)@(posedge interface.clk);interface.c 1;vpiw.pass if sva succeeded("MULTITHREAD ASSERT","The assertion should have succeeded!");end Accellera Systems Initiative45

Multi-threadantecedent/consequent (contd.) a ##[1:4] b - ##[1:3] crepeat (test loop count) begin// Generate invalid delays for asserting b and c signalsrandomize(delay for b inside {0, [1:4], [5:10]}, delay for c inside {0,[4:10]});interface.a 1;repeat (delay for b)@(posedge interface.clk);interface.b 1;if (delay for b 5)vpiw.pass if sva not succeeded("MULTITHREAD ASSERT","The assertion should have failed!");repeat (delay for c)@(posedge interface.clk);interface.c 1;if (delay for b inside [1:4])vpiw.fail if sva succeeded("MULTITHREAD ASSERT","The assertion should have failed!");end Accellera Systems Initiative46