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P04Outcome of Technical Review and Recent ProgressDavid Stuart, UC Santa BarbaraFermilab Director’s Review19 March 2019

Outline Outcome of the MTD Technical Review Recent Technical Progress Optimized BTL crystal geometry Design of BTL Concentrator Card R&D for BTL SiPMs Design of ETL Readout ASIC Design of ETL module assembly SummaryDavid StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 20192

Charge #2MTD Technical Review 15-16 Nov.Technical Review committee:Jarek Kaspar, U. WashingtonMitch Newcomer, U. PennsylvaniaMark Oreglia, U. ChicagoRob Roser, Fermilab (chair)Charged to assess physics requirements, technical design andits maturity, R&D plan, organization and risks, anddocumentation (CDR).Committee’s report is positive on all charge items.Committee provided specific recommendations:David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 20193

Charge #8Technical Review recommendations ETL-R1: It is crucial to follow the schedule of beam testand/or system integration tests to verify functionality ofthe LGAD/ROC/Back-end systems We are planning a series of tests aimed at each majordevelopment stage Will examine the mechanical, thermal, and electricalperformance of modules Will use realistic backend electronics as it becomesavailable Test full sensor-to-DAQ chain with multiple modules Beam tests to verify the production modules.David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 20194

Charge #8Technical Review recommendations BTL-R1: It is crucial to follow the schedule of beam testand/or system integration tests to verify functionality ofthe readout unit and compatibility with the other systems. Initial beam and system tests planned with sensor-loadedreadout units Continue these tests through to final prototype, preproduction, and production stages.David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 20195

Charge #8Technical Review recommendations ETL & BTL: It is crucial to follow the schedule of beamtest and/or system integration tests Series of dedicated test beams planned, and we are alsonow running in a long term, parasitic-mode at FTBF, withdevices left downstream in cold box.Cold boxDAQSi Xie (Caltech), Paolo Meridiani (Rome), Marco Lucchini (Princeton), and Ryan Heller (FNAL) in the Fermilab test beamDavid StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 20196

Charge #8Technical Review recommendations ETL-R2: Identify alternative ASIC solutions from existing orpotentially viable prototypes of other systems, and createa decision matrix for breakpoints in the ETLROCdevelopment in case that device falls behind in thedevelopment schedule or fails to function as required. Potential use of alternative ASIC solutions comes in twoways: as a ROC to use for early sensor and moduleprototyping, and as a ROC to use for production of thefinal detector. For early prototyping, we have designed test boards usingthe SKIROC2 ASIC to read out large prototype LGAD sensorsand test bump-bonding performance with sensors bondedto interposers.David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 20197

Charge #8Technical Review recommendations ETL-R2: Identify alternative ASIC solutions from existing orpotentially viable prototypes of other systems, and createa decision matrix for breakpoints in the ETLROCdevelopment in case that device falls behind in thedevelopment schedule or fails to function as required. Potential use of alternative ASIC solutions comes in twoways: as a ROC to use for early sensor and moduleprototyping,and asLGADa ROC to use for production of the96-channelfinal detector.bump-bonded toPCB for wire bonding For early prototyping, we have designed test boards usingthe SKIROC2 ASIC to read out large prototype LGAD sensorsand test bump-bonding performance with sensors bondedto interposers.David StuartSKIROC2-CMS based readout board,modified from HGCAL test boardsP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 20198

Charge #8Technical Review recommendations ETL-R2: Identify alternative ASIC solutions from existing orpotentially viable prototypes of other systems, and createa decision matrix for breakpoints in the ETLROCdevelopment in case that device falls behind in thedevelopment schedule or fails to function as required. Potential use of alternative ASIC solutions comes in twoways: as a ROC to use for early sensor and moduleprototyping, and as a ROC to use for production of thefinal detector. Considering use of the ATLAS HGTD ALTIROC prototypes. Discussed with HGTD PM and plan for shared testing. Close collaboration on sensor prototyping in beam tests.David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 20199

Charge #8Technical Review recommendations ETL-R2: Identify alternative ASIC solutions from existing orpotentially viable prototypes of other systems, and createa decision matrix for breakpoints in the ETLROCdevelopment in case that device falls behind in thedevelopment schedule or fails to function as required. For the production phase, the ALTIROC could be a viable alternative ifit meets our specs for power and time resolution for small signals andit turns out that the ETL ROC does not. Discussions between design teams have shared progress, and theresults from the 1st ALTIROC prototype informed the improvementsimplemented in the ETL ROC design. We will continue these discussions, and feedback will help optimizeeach of the designs for their respective needs and mitigate risks. If either encounters functional problems, these discussions will easecross-adoption of designs. Decision points are set by the prototyping schedule; the first ETL ROCprototype with all stages will be measured next year.David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 201910

Charge #8Technical Review recommendations ETL-R3: Identify criteria for acceptable SEE rates in theETLROC and possible error mitigation schemes. Corruption of data bits has a negligible effect. For configuration bits, we are incorporating the standardTriple Modular Redundancy approach. Correlated effects are suppressed by separating replicasspatially; investigating time delays for further suppression. To correct bit flips, we will use RD53 “trickle reconfiguration” Impact on efficiency will be simulated to specify the criteria,and we are considering ways to measure rates with ion beamsDavid StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 201911

Charge #8Technical Review recommendations BTL-R3: Consider setting granularity of number of chips/card so that one DC-DC converter is matched to a singleTOFHIR readout card. The current design incorporates this by assigning a singleDC-DC converter per TOFHIR readout card, with anothertwo converters used to power the Concentrator Card.David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 201912

Charge #8Technical Review recommendations BTL-R4: Develop a plan for powering up the ASICs cardsconnected to the concentrator card and for exploiting thelpGBT capabilities for control and environmentalmonitoring. We are developing a powering plan using the GBT SCAoutput pins to control enabling of each DC-DC converter. The GBT SCA inputs will be used to monitor the power status input and output voltages concentrator card temperature SiPM temperatures SiPM bias currentsDavid StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 201913

Charge #8Technical Review recommendations BTL-R2: In P6, identify the external dependencies such aslpGBT, DC-DC converter, and ETH manufacturing of theDC-DC converter board. We have a watch list of the external deliverables. Included in the P6 schedule with links to the dependentactivities. Assigned contacts responsible for monitoring their progress.David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 201914

Charge #8Technical Review recommendations R1: Continue on your plan to achieve CD-1 this comingApril We will.David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 201915

Recent technical progressDavid StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 201916

Details in MTD-BO 1Optimization of BTL geometryTiles Since TR, we’ve completed the BTL geometry optimization. Studied tile vs bar option.Bars8x8x3 mm3x3x57 mm Improved time resolution Uniform time vs position Occupancy increased, but still low.David Stuart3.2thr 100 mVt(Left)V(bias) 72 Vt(Right)t(Ave)32.82.6Time Resolution [ps] Two measurements/hitt(i) - t(MCP) [ns] Bar geometry selected in Dec.3LYSO:Ce 3x3x50 mm - HPK 3x3 mm2 (15 µm)903LYSO:Ce 3x3x50 mm - HPK 3x3 mm2 (15 µm)80thr 100 mVt(Left)V(bias) 72 Vt(Right)70t(Ave)605040302.420102.2P04: Outcome of Technical Review and Recent Progress 100102030400Hodoscope X [mm]Fermilab Director’s Review10010203040Hodoscope X [mm]19 March 201917

Details in MTD-BO 3Design of Concentrator Card Design and production of concentrator card is a US CMSdeliverable; significant progress since last JuneDC-DC converterDavid StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 201918

Details in MTD-BO 3Design of Concentrator Card Design and production of concentrator card is a US CMSdeliverable; significant progress since last June Power-only prototype in hand Prototype this summer. Details in Yurii Maravin's talk in tomorrow’s breakout.David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 201919

Details in MTD-BO 2SiPM R&D R&D and procurement of SiPMs is a US CMS deliverable;significant progress since last June New devices from HPK and FBK tested before and afterirradiation and annealing. Details in Mitch Wayne's talk in tomorrow’s breakout.David StuartP04: Outcome of Technical Review and Recent ProgressFermilab Director’s Review19 March 201920

Details in MTD-BO 5ETL Readout ASIC progress Design of the ETL ROC is a significant US CMS deliverable. Design challenge is extracting TOA of signals, which can be small( 5 fC) after dose, within constrained power budget. ASIC block diagram developed.Design from scratch (none)Base on designs in 130 nm Based on existing IP blocks.Based on existing designconcept or design in 65nmfrom other on-going projectsBased on designs alreadyavailable in 65 nm criminatorMemoryTOTTDCChargeInjectionDAC forthresholdcorrectionPLLDavid StuartSerializer16 X 16ElinkTxPulseInjectionPhaseShifterI2CP04: Outcome of Technical Review and Recent ProgressFastControlFermilab Director’s Review19 March 201921

Details in MTD-BO 5ETL Readout ASIC progress Significant progress on design of all building blocksBUF Blocks critical to time resolution performance completed.arge injectioncharge injectionDiagnosticReadoutBUFPreAmpTDCmp PadDiagnosticNormalReadoutReadoutPreAmp100%TDCBump PadDACCircularBufferDavid erationProgressLegendeLink RxeLinkTxClockPLLGenerationeLink hifterI2CP04: Outcome of Technical Review and Recent ProgressI2CFermilab Director’s Review19 March 201922

Details in MTD-BO 5ETL Readout ASIC progress Critical preamp discriminator stages complete and performwell in simulation. Meets spec of 50 ps/hit 35 ps / 2-hit trackcharge injectionBUFlow power mode at max fluenceDiagnosticReadoutPreAmpTDCBump 4ReferenceGenerationDavid StuarteLinkTxeLink RxP04: Outcome of Technical Review and Recent Progress2highPhasepower mode at max fluenceShifterFermilab Director’s Review19 March 201923