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Si53154PCI-E XPRESS G EN 1, G EN 2, G EN 3, AND G EN 4 Q UADF ANOUT B UFFERFeatures PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clockcompliant Supports Serial ATA (SATA) at 100 MHz 100–210 MHz operationLow power, push pull, differential output buffersInternal termination for maximum integration Dedicated output enable pin foreach outputFour PCI-Express buffered clockoutputsClock input spread tolerableSupports LVDS outputsI2C support with readbackcapabilitiesExtended temperature:–40 to 85 C3.3 V power supply24-pin QFN packageOrdering Information:See page 17.Applications24222120SCLK19VDD118 OE3*OE1*217 VDDVDD3VSS4OE2*5VDD616 DIFF325GND15 DIFF314 DIFF289101112DIFF0DIFF0DIFF1DIFF1VDD13 DIFF27OE0*The Si53154 is a spread spectrum tolerant PCIe clock buffer that can sourcefour PCIe clocks simultaneously. The device has four hardware output enablecontrol inputs for enabling the respective differential outputs on the fly. Thedevice also features output enable control through I2C communication. I2Cprogrammability is also available to dynamically control skew, edge rate andamplitude on the true, compliment, or both differential signals on the clockoutputs. This control feature enables optimal signal integrity as well asoptimal EMI signature on the clock outputs. Measuring PCIe clock jitter isquick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it forfree at nSDATAWireless access point RoutersDIFFINPin Assignments VSSNetwork attached storage Multi-function printersDIFFIN *Note: Internal 100 kohm pull-up.Patents pendingFunctional Block ntrol & MemoryControlRAMOE [3:0]Rev. 1.3 4/16Copyright 2016 by Silicon LaboratoriesSi53154

Si531542Rev. 1.3

Si53154TABLE O F C ONTENTSSectionPage1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72.1. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72.2. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72.3. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105. Pin Descriptions: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Rev. 1.33

Si531541. Electrical SpecificationsTable 1. DC Electrical SpecificationsParameterSymbolTest ConditionMinTypMaxUnit3.3 V Operating VoltageVDD core3.3 5%3.135—3.465V3.3 V Input High VoltageVIHControl input pins2.0—VDD 0.3V3.3 V Input Low VoltageVILControl input pinsVSS – 0.3—0.8VInput High VoltageVIHI2CSDATA, SCLK2.2—–VInput Low VoltageVILI2CSDATA, SCLK——1.0VInput High Leakage CurrentIIHExcept internal pull-downresistors, 0 VIN VDD——5 AInput Low Leakage CurrentIILExcept internal pull-upresistors, 0 VIN VDD–5—— A3.3 V Output High Voltage(Single-Ended Outputs)VOHIOH –1 mA2.4——V3.3 V Output Low Voltage(Single-Ended Outputs)VOLIOL 1 mA——0.4VHigh-impedance OutputCurrentIOZ–10—10 AInput Pin �—35mAOutput Pin CapacitancePin InductanceDynamic Supply Current inFanout Mode4IDD 3.3VDifferential clocks with 5”traces and 2 pF load,frequency at 100 MHzRev. 1.3

Si53154Table 2. AC Electrical t100—210MHz0.6—4V/nsDIFFIN at 0.7 VInput Frequency RangeRising and Falling SlewRates for Each Clock OutputSignal in a Given DifferentialPairfinTR / TFSingle ended measurement: VOL 0.175 to VOH 0.525 V (Averaged)Differential Input HighVoltageVIH150——mVDifferential Input LowVoltageVIL——–150mVCrossing Point Voltage at0.7 V SwingVOXSingle-ended measurement250—550mVVcross Variation over allEdges VOXSingle-ended ��—psAbsolute Maximum InputVoltageVMAX——1.15VAbsolute Minimum InputVoltageVMIN–0.3——VDuty Cycle for Each ClockOutput Signal in a GivenDifferential PairTDCMeasured at crossing point VOX45—55%Rise/Fall MatchingTRFMDetermined as a fraction of2 x (TR – TF)/(TR TF)——20%Duty CycleTDCMeasured at 0 V differential45—55%Clock SkewTSKEWMeasured at 0 V differential——50psAdditive Peak JitterPk-Pk0—10ps10 kHz F 1.5 MHz0—0.5ps1.5 MHz F Nyquist Rate0—0.5psIncludes PLL BW 2–4 MHz(CDR 10 MHz)0—0.10psDifferential Ringback VoltageTime before RingbackAllowedDIFF at 0.7 VAdditive PCIe Gen 2 PhaseJitterRMSGEN2Additive PCIe Gen 3 PhaseJitterRMSGEN3Notes:1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.Rev. 1.35

Si53154Table 2. AC Electrical Specifications ditive PCIe Gen 4 PhaseJitterRMSGEN4PCIe Gen 4——0.10psAdditive Cycle to Cycle JitterTCCJMeasured at 0 V differential—2050psLong-term AccuracyLACCMeasured at 0 V differential——100ppmRising/Falling Slew rateTR/TFMeasured differentially from 150 ing Point Voltage at0.7 V SwingVOXEnable/Disable and SetupClock Stabilization fromPower-UpTSTABLEStopclock Set-up TimeTSSMeasured from the point when bothVDD and clock input are validNotes:1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.Table 3. Absolute Maximum ConditionsParameterSymbolConditionMinTypMaxUnitVDD 3.3VFunctional——4.6VInput VoltageVINRelative to VSS–0.5—4.6VDCTemperature, StorageTSNon-functional–65—150 CIndustrial Temperature, OperatingAmbientTAFunctional–40—85 CCommercial Temperature, OperatingAmbientTAFunctional0—85 CTemperature, JunctionTJFunctional——150 CDissipation, Junction to CaseØJCJEDEC (JESD 51)——25 C/WDissipation, Junction to AmbientØJAJEDEC (JESD 51)——37 C/WESDHBMJEDEC (JESD 22 - A114)2000—–VUL-94UL (Class)Main Supply VoltageESD Protection (Human Body Model)Flammability RatingV–0Note: Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supplysequencing is not required.6Rev. 1.3

Si531542. Functional Description2.1. OE Pin DefinitionThe OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OEpin needs to be logic high and the I2C output enable bit needs to be logic high. There are two methods to disablethe output clocks: the OE is pulled to a logic low, or the I2C enable bit is set to a logic low. The OE pins are requiredto be driven at all times even though they have an internal 100 k resistor.2.2. OE AssertionThe OE signals are active high inputs used for synchronous stopping and starting the DIFF output clocks respectivelywhile the rest of the clock generator continues to function. The assertion of the OE signal by making it logic highcauses stopped respective DIFF outputs to resume normal operation. No short or stretched clock pulses areproduced when the clock resumes. The maximum latency from the assertion to active outputs is no more than twoto six output clock cycles.2.3. OE DeassertionWhen the OE pin is deasserted by making it logic low, the corresponding DIFF output is stopped, and the final outputstate is driven low.Rev. 1.37

Si531543. Test and Measurement SetupFigures 1–3 show the test load configuration for differential clock signals.Figure 1. 0.7 V Differential Load ConfigurationFigure 2. Differential Measurement for Differential Output Signals(for AC Parameters Measurement)8Rev. 1.3

Si53154VMIN –0.30VVMIN –0.30VFigure 3. Single-Ended Measurement for Differential Output Signals(for AC Parameters Measurement)Rev. 1.39

Si531544. Control Registers4.1. I2C InterfaceTo enhance the flexibility and function of the clock buffer, an I2C interface is provided. Through the I2C Interface,various device functions are available, such as individual clock output enable. The registers associated with the I2CInterface initialize to their default setting at power-up. The use of this interface is optional. Clock device registerchanges are normally made at system initialization, if any are required. Power management functions can only beprogramed in program mode and not in normal operation modes.4.2. Data ProtocolThe I2C protocol accepts byte write, byte read, block write, and block read operations from the controller. For blockwrite/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with theability to stop after any complete byte is transferred. For byte write and byte read operations, the system controllercan access individually indexed bytes.The block write and block read protocol is outlined in Table 4 while Table 5 outlines byte write and byte readprotocol. The slave receiver address is 11010110 (D6h).Table 4. Block Read and Block Write lock Write ProtocolDescriptionStartSlave address–7 bitsWriteAcknowledge from slaveCommand Code–8 bitsAcknowledge from slaveByte Count–8 bitsAcknowledge from slaveData byte 1–8 bitsAcknowledge from slaveData byte 2–8 bitsAcknowledge from slaveData Byte/Slave AcknowledgesData Byte N–8 bitsAcknowledge from 755:4856.Rev. 1.3Block Read ProtocolDescriptionStartSlave address–7 bitsWriteAcknowledge from slaveCommand Code–8 bitsAcknowledge from slaveRepeat startSlave address–7 bitsRead 1Acknowledge from slaveByte Count from slave–8 bitsAcknowledgeData byte 1 from slave–8 bitsAcknowledgeData byte 2 from slave–8 bitsAcknowledgeData bytes from slave/AcknowledgeData Byte N from slave–8 bitsNOT AcknowledgeStop

Si53154Table 5. Byte Read and Byte Write ProtocolBit18:291018:111927:202829Byte Write ProtocolDescriptionStartSlave address–7 bitsWriteAcknowledge from slaveCommand Code–8 bitsAcknowledge from slaveData byte–8 bitsAcknowledge from slaveStopBit18:291018:11192027:21282937:303839Rev. 1.3Byte Read ProtocolDescriptionStartSlave address–7 bitsWriteAcknowledge from slaveCommand Code–8 bitsAcknowledge from slaveRepeated startSlave address–7 bitsReadAcknowledge from slaveData from slave–8 bitsNOT AcknowledgeStop11

Si53154Control Register 0. Byte NameTypeReset settings 00000000BitNameFunction7:0ReservedControl Register 1. Byte 1BitD7D6D5D4D3NameTypeDIFF0 OER/WR/WR/WR/WR/WReset settings 00000101BitName7:3Reserved2DIFF0 OEFunctionOutput Enable for DIFF0.0: Output disabled.1: Output enabled.1Reserved0DIFF1 OEOutput Enable for DIFF1.0: Output disabled.1: Output enabled.12Rev. 1.3R/WDIFF1 OER/WR/W