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White Paper: Virtex-4 FPGARWP233 (v1.0) October 19, 2005IEEE 802.17, Resilient PacketRing Networks Enabled byFPGAsBy: Nick PossleyResilient Packet Ring (RPR) is a transport technologythat has been available for several years. Thestandard IEEE 802.17 specifies the transport. Thistransport technology provides a wide range ofservices that are just now becoming very importantto the industry for deployment of IP basedmultimedia services.Demand for this technology is increasing, and Xilinxhas invested in a supported reference design thatutilizes the Virtex -4 family of FPGAs to create acomplete RPR MAC solution for equipmentvendors. The solution includes hardware andsoftware that provides full compliance to IEEE802.17.This paper describes RPR as a network, explainshow the MAC operates to provide required networkfunctionality, gives a high-level view of the Virtex-4implementation of the MAC including device sizing,and covers a few system design use cases. 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.All other trademarks are the property of their respective owners.WP233 (v1.0) October 19, 2005www.xilinx.com1
RBackgroundWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsLegacy communication systems are heavily deployed with ring topologies. DS1 andDS3s are often deployed in rings with ring switches. More recently, SONET/SDH isbased on rings including the Bidirectional Line Switched Ring (BLSR) and theUni-Directional Path Switched Ring (UPSR), the most commonly used ringarchitectures. These SONET/SDH rings already have fiber in place. Also, these ringarchitectures provide 50 ms protection switching in network failure scenarios in mostcases. As a result, a certain level of network availability is achieved and expected.One problem with SONET/SDH is that bandwidth is wasted in order to provideprotection, and because it is channelized, no statistical multiplexing gain can beachieved between channels. This leads to network inefficiencies because unusedbandwidth on one channel cannot be utilized by another channel.Resilient Packet Ring (RPR) is a transport technology specified by IEEE specification802.17. This technology provides the best of both worlds. It provides 50 ms protectionswitching for high network availability while having a packet-based transport thatuses statistical multiplexing gain to better utilize all available bandwidth, includingprotection bandwidth. Further, RPR provides several levels of Quality of Service (QoS)guarantees, including QoS sufficient to support any type of TDM service transportedover packets. Packets have become, by far, the most dominant traffic; RPR is thereforethe most efficient transport technology for both packet and TDM traffic services goingforward.In addition, RPR is a ring topology, so it can easily be adapted to existing fiber plantsthat are deploying SONET/SDH. Also, service providers' familiarity with ringnetworks makes RPR a good solution for transitioning from a TDM-based network toa packet-based network.ApplicationsRPR can be used in a variety of ways to distribute a variety of services. The most recent"buzz" about "triple play" services touts RPR as a perfect match for aggregation ofservice traffic in metropolitan areas.Triple Play services include Voice, Video, and Data. There are nuances to each of theseservices. Voice services can include real-time voice traffic, e.g., phone call, ornon real-time, streaming music distribution. Video services traditionally includestreaming video distribution, e.g., Video On Demand. Video services can also includevideo teleconferencing, which is a real-time service. These differences in servicesrequire different levels of QoS from the transport mechanism in the network.RPR works well to provide all of these services due to its defined service primitives inIEEE 802.17. These service primitives are: Class A Service - Provides an allocated, guaranteed data rate with low end-to-enddelay and jitter bound. This class has precedence over all other classes.Class B Service - Provides an allocated, guaranteed data rate with boundedend-to-end delay and jitter for the allocated rate. This class also provides access tounallocated bandwidth that has no guaranteed data rate or bounded delay andjitter. The primitives referring to the different used bandwidths are Class BCommitted Information Rate (classB-CIR) and Class B Excess Information Rate(classB-EIR). Class B takes precedence over class C.Class C Service - Provides a best effort delivery with no guaranteed data rate andno bounded delay or jitter.Given this set of services, it is clear that all real-time services for Voice or Video will useClass A in order to maintain the lowest latency and guaranteed bandwidth. Streamingvideo or streaming voice distribution would use Class B. Data services would use2www.xilinx.comWP233 (v1.0) October 19, 2005
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsclass C. Of course, these pairings all depend on what a service provider is offering.Some service providers might provide Class B data services for those customerswilling to pay more. For consumer services, the breakdown described above is themost accurate because it provides the most efficient use of the available networkbandwidth.RPR can support multiple rates; 1G, 2.5G, and 10G are the standard rates. This allowsfor scaling of the technology to accommodate a growing network. 1G transport uses aGigabit Ethernet physical layer. 2.5G transport uses a SONET OC48 physical layer.10G uses a SONET OC-192 or 10GE physical layer.Metro NetworksFigure 1 is a network diagram of an RPR metro network.V5.2STM1/4COTRouterCOTRPR 1BRASCOTRPR 2RPR 3COTRPR 4WP233 01 01 091305Figure 1:RPR Metro NetworkThis is an example network that illustrates how RPR is deployed and the types ofequipment used for the deployment.xPON and VDSL are the upcoming delivery mechanisms for triple play services. Thisplaces RPR in OLT equipment for PON and in DSLAMs for VDSL. Of course, manyequipment vendors are producing one platform to do both, which is typically dubbedan MSPP (Multiservice Provisioning Platform).In addition, there is a Central Office Terminal that must connect the metro network tothe core or regional network. This terminal must also support RPR. The types ofequipment in this category vary from edge routers to core switches.The metro space is sometimes required to provide a mixture of TDM and packetservices. RPR works well in these scenarios; it can easily be mapped into a VCATtunnel inside of a SONET stream, which is a subset of the available bandwidth. TDMservices can be mapped onto the extra bandwidth. This is probably most desirablewhen networks are being upgraded, and legacy services must be maintained.TDM services can also be mapped onto RPR using a pseudo-wire-type approachsimilar to PWE-3. This allows for all services to be transported across an RPR ring.WP233 (v1.0) October 19, 2005www.xilinx.com3
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsWireless BackhaulAnother interesting application for RPR is transport for wireless backhaul networks.RPR's service classes work well for guaranteeing the low latency required for real-timevoice services. Figure 2 shows a potential network based on the UMTS networkarchitecture and RPR.PublicNetworkNode BNode B1GRPR RingRNCGGSN2.5/10 GRPR RingNode BSGSNPicocell1GRPR RingPicocellPicocellWP233 02 0913 05Figure 2:RPR Wireless Backhaul NetworkRPR can remove much of the complexity in the Iu'x' interfaces because it incorporatesthe QoS transport service into the L2 transport instead of inside ATM PVCs that arebandwidth inefficient.A common application scenario is MPLS over RPR. Using static LSP, MPLS canprovide the secondary address for application ports that are transported over RPR.Overall, these applications show that RPR has a wide market space and can play a keyrole in services moving forward.One thing to note is the lack of RPR technology available in order to enable thedeployment of the standard. FPGAs are an ideal device to support RPR if an efficientimplementation that doesn't make the technology cost prohibitive can be achieved.RPR MAC4The RPR MAC is the central component that enables RPR transport. This MACgoverns all access to the ring. The MAC fits into the OSI reference model as shown inFigure 3.www.xilinx.comWP233 (v1.0) October 19, 2005
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsOSI ReferenceModel LayersRPR LayersHigher LayersApplicationPresentationLogical Link Control (MAC Client)SessionMAC ControlTransportFairnessTopology andProtectionMAC ServiceInterfaceOAMNetworkPHY ServiceInterfaceMAC DatapathData LinkPhysical LayerPhysicalMediumWP233 03 091405Figure 3:RPR Relationship to the OSI Reference ModelOverviewFunctionally, the MAC has the following aspects: Network ProtectionData Formatting and TransportQoSOAMPNetwork Protection requires the MAC to track the topology of the network andrespond to any changes via steering and wrapping of datapaths. Figure 4 shows thearchitecture for this functionality.MA CONTROL.requestMA DATA.requestMA CONTROL.indicationMA DATA.indicationMAC Service InterfaceMACcontrolMAC Control SublayerMAC Datapath Sublayerringlet selectionringlet0 datapathringlet1 datapathReceiveTransmitPHY Service InterfaceWP233 04 091405Figure 4:WP233 (v1.0) October 19, 2005RPR Protection Path Architecturewww.xilinx.com5
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by a formatting and transport requires the MAC to service client requests fortransport by framing the data into the RPR packet format and resolving the hop countin the transmit direction. In the RX direction, the MAC is required to receive and passalong any packets not meant for the local station. For those packets addressed to thelocal station, the MAC parses, receives the data, and passes it to the client interface.Figure 5 shows the functionality for single and dual queue MAC ssB/CTo Other DatapathSingle Queue MACTo Other DatapathDual Queue MACWP233 05 091405Figure 5:RPR Datapath ArchitectureQoS requires the MAC to monitor the topology of the network and the resourceutilization in the network and to perform traffic policing/shaping for the variouslevels of quality based on available resources. Dual queue versus single queue simplymeans whether or not a secondary set of queues is in the MAC. A dual queue MACsupports class B/C traffic classes; whereas, a single queue only supports class A(Figure 5). QoS requires a fairness algorithm to determine the utilization of networkresources and to allocate the correct amount of bandwidth to the service classes.Figure 6 shows how the fairness algorithm allocates bandwidth.6www.xilinx.comWP233 (v1.0) October 19, 2005
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsS1S26 Mb/s 5 Mb/sS32 Mb/sS1S2S36 Mb/s 5 Mb/s 2 Mb/swwwS1S2S36 Mb/s 5 Mb/s 2 w1 Mb/s2 Mb/s4 Mb/s4 Mb/s10 Mb/sCapacity4 Mb/s10 Mb/sCapacity6 Mb/s5 Mb/s4 Mb/sUnregulated Access(Theoretical)10 nessWP233 06 091505Figure 6:RPR Fairness ExampleOAMP requires the MAC to gather statistics for each of the services and report thedata back to the user via a standardized interface, e.g., MIB. In addition, the MAC isrequired to provide provisioning of all relevant parameters for each station.For more details, please refer to the IEEE 802.17 latest specification.ImplementationFrom the previous sections, it is obvious that the MAC is comprised of a complex setof functions. Given the complexity, it would make sense for this to be a largeimplementation, but Xilinx has not only implemented a most efficient and highperformance design, the design is also half the price of any competing design. Thisimplementation has been made possible by the Virtex-4 family of FPGAs. Through theuse of the DSP48 slices and the speed improvements, the Virtex-4 FPGA providesunique ways to converge more functionality into less logic.The implementation has a split between HW and SW in which all real time functionsare implemented in hardware and everything else in software. This has resulted in adesign that is only 11000 slices and 80 block RAMs for 1G and 2.5G. It will be slightlylarger for 10G only to accommodate a wider memory interface. Table 1 shows thesizing.Table 1:RPR MAC FPGA SizingLogic BlockApprox. Slice Count forBoth RingsApprox.Block RAMsDCMsDSP SlicesPHY Interface (SPI, GMII, XGMII)25042–RX Datapath2000201–2–Transmit Datapath120018––Client Datapath100081–Control Path100061–WP233 (v1.0) October 19, 2005www.xilinx.com7
RTable 1:White Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsRPR MAC FPGA Sizing (Continued)Approx. Slice Count forBoth RingsApprox.Block RAMsDCMsDSP SlicesFairness Block30001–40Topology Block18006––Memory Management6005–201–2–Others (Self Test, Timer, etc.)2001––11,00072–876–840Logic BlockTotalThe design requires at least 15,000 slices (actual logic may need 10,500 to 12,000 slices,and 20% head room must be kept for client interface customizations), 8 DCMs,RocketIO interfaces (either 3.125 Gb/s for XAUI or 10 Gb/s for XSBI), and 40–45DSP slices are required for the design. Regarding IO calculations, the 10 Gb/sinterface needs max IO signals, 200 signals for memory interface, and 100 signalsfor system. If the PHY interfaces are non-serial, IO requirements are even higher. IfRocketIO is used as the interface to the PHY, a 350-I/O pin device is estimated for thedesign.The DSP48 slices available in all Virtex-4 family devices allow the fairness block to bevery small. This is a major contribution to the compact nature of the design.In addition, the solution is customizable to a customer's exact application, withoutcharging for any extra silicon. Figure 7, Figure 8, and Figure 9 show the block diagramfrom different aspects.SoftwareMIB HandlerAdmin InterfaceClientDatapathFairness Instance 1Receive DatapathRing 1Transmit DatapathRing 1OAM HandlerTopologyControllerMemoryManagementStation ManagementControlPathFairness Instance 0Receive DatapathRing 0PHY Interface 1Transmit DatapathRing 0PHY Interface 2FPGAWP233 07 091505Figure 7:8RPR MAC FPGA HW/SW Splitwww.xilinx.comWP233 (v1.0) October 19, 2005
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsClientData PathClientControl(Optional)AddressLookupMemory BlockFor Ring 1StorageRPR Core in FPGAMemory BlockFor DatapathStorageMemory BlockFor Ring 0StoragePHY 0PHY 1WP233 08 091405Figure 8:WP233 (v1.0) October 19, 2005RPR MAC FPGA Black Box HW Viewwww.xilinx.com9
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsDevice Driver(In Software)Client Data PathClient ControlPathRegistersDDR Controller(1 to 3 ntFairnessBlockTX FIFO2KTopologyControllerRX FIFO2KRX FIFO2KBufferManagementTX FIFO2KTX ClientFIFORX Datapath Ring 0TX Datapath Ring 0CenterWap InputTX Datapath Ring 1CenterWap InputSteerPathEdgeWapInputFIFO 2K32 Bits WideSteerPathRX Datapath Ring 1EdgeWapWrap Mux3 to 1 Type, 32 BitsFIFO 2K32 Bits WideInputWrap Mux3 to 1 Type, 32 BitsFIFO 2K32 Bits WideFIFO 2K32 Bits WideWP233 09 091505Figure 9:RPR MAC FPGA Detailed Internal ArchitectureThere are several different ways to view the core, and they each provide varying levelsof detail.Table 2 shows the customer implementation options.10www.xilinx.comWP233 (v1.0) October 19, 2005
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsTable 2:RPR MAC FPGA Implementation OptionsPossibilities1G Ethernet10G EthernetOC48OC192RocketIO, parallelXAUI or XSBI(RocketIO)SPI 3.0SPI 4.21 block for Ring 0,Ring 1, and datapath1 block for Ring 0,1block for Ring 1, and1 block for thedatapath (3 total)1 Block for Rings and1 for data Path1 block for Ring 0, 1block for Ring 1, and 1block for the datapath(3 total)32643264Client DatapathLVDS, parallel, GbERocketIO, parallel (64bits)SPI 3.0, LVDSSPI 4.2Client Control Path32-bit parallel,embedded CPU,merge with datapath32-bit parallel,embedded CPU,merge with datapath32-bit parallel,embedded CPU,merge with datapath32-bit parallel,embedded CPU,merge with datapathPHY 0 and PHY 1(GMII)MemoryMemory Bus WidthThe Virtex-4 FX family provides the advantage of integrated PHYs for all interfacesexcept OC192. This allows for further integration of functionality inside the FPGAand, hence, less overall system cost.For most customer systems, availability of the network is one of the most importantfactors to consider. RPR provides high availability through its network protectionmechanisms. Most equipment vendors also require some equipment protection forhigher availability and maintenance. The RPR core provides for equipment protectionvia a MATE interface and some software/hardware functionality. Figure 10 shows theMATE interface.WP233 (v1.0) October 19, 2005www.xilinx.com11
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsControl I/FControl singTopology, FairnessOAMMATEI/FLocalData I/FFrameProcessingMATEI/FDatapath (Ring 1)Datapath (Ring 1)Datapath (Ring 1)PHY I/FBuffer ManagerTopology, FairnessOAMLocalData I/FDatapath (Ring 1)PHY I/FPHY I/FBuffer ManagerPHY I/FExternal StorageExternal StorageCard 1 (Secondary)Card 2 (Primary)Shaded Blocks will be put in Suspend/Watch Mode in MATE I/FWP233 10 091505Figure 10:RPR MAC FPGA Equipment ProtectionIn Figure 10, there is a datapath interface and a control path interface between theMACs. The datapath interface allows for protection of PHY failures independent ofMAC failures. In order to do this, the control of the MAC needs to remain on onecontroller. This requires a master/slave state machine between the two controllers.Also, if the whole MAC fails, then the functionality shown on a single card (see Fig. 10)is switched over.The RPR MAC also has many options for pinouts. Table 3 shows a few scenarios.Table 3:RPR MAC FPGA Pinnout ExamplesFunctional BlockMemoryPHYDatapathControl and OtherGbE with RocketIO and RocketIOdatapath interface (single cardimplementation). External CAM.50104–890GbE parallel interface to the PHY(line side), GbE backplaneinterface (client side). ExternalCAM.50482490OC48 with SPI3.0 interface to PHYand backplane as RocketIO 3.125G1001604–89010G with XAUI RocketIO interfaceto PHY, parallel to backplane.2601814090OC48 with MATE interface, SPI3.0PHY interface.10080 20 for MATE8 for RocketIO9012www.xilinx.comWP233 (v1.0) October 19, 2005
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsTestingOf course, compliance testing to the IEEE 802.17 specification is the "real" test. Table 4is the compliance matrix based on test cases.The subclause number refers to IEEE 802.17 specification subclauses, and the namerefers to Protocol Implementation Conformance Statement (PICS), outlined at the endof every section of the IEEE 802.17 specification.Table 4:RPR MAC Compliance MatrixSubclauseNameDetailsSupportTest Case Ref6.3FTS1Generation of Strict FramesYesRPR-00056.3FTS2Generation of Relaxed framesYesRPR-00066.4.1SP1MA Data RequestYesCDT-00026.4.2SP2MA Data IndicationYesCDR-00016.4.3SP3MA Control RequestYesInternal.6.4.4SP4MA Control IndicationYesInternal.7.5.3SM1Idle ShaperYesCCT-00047.5.4SM2MAC Control ShaperYesCCT-00017.5.5SM3Class A ShaperYesCCT-00027.5.6SM4Class B ShaperYesCCT-00037.5.7SM5Fairness Eligible ShaperYesTXP-0001, 00027.5.8SM6Downstream ShaperYesTXP-0001, 00027.6.3.5SM7Receive Frame EdgeYesRXD-0014SM8Receive CheckYesRXD-0003SM9Receive CountYesRXD-0023, RXD-0024SM10Receive StripYesRXD-0027Chapter 6Chapter 77.6.3.12SM11Receive AdjustYesRXD-0030SM12Receive FilterYesRXD-0032SM13Receive Filter Data CountYesRXD-0023 - 27SM14Receive Filter Control CountYesRXD-0023 - 277.6.4SM15Wrong RingletYesRXD-00137.7.1SM16Ringlet SelectionYesCDT-00027.7.4SM17Stage Q selectionYesCDT-00057.7.5SM18Data Add CountYesTXP-0004SM19Control Add CountYesTXP-0004SM20aSingle Q TransmitYesTXP-0001SM20bDual Q TransmitYesTXP-0002SM21Transmit CountYesTXP-00047.67.10SM22Transmit RouteYesTXP-00047.4DP1Transit DelayYesRPR-0013 and P-00037.4.4PM2aCenter WrappingYesTXP-0003WP233 (v1.0) October 19, 2005www.xilinx.com13
RTable 4:White Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsRPR MAC Compliance Matrix (Continued)SubclauseNameDetailsSupportTest Case Ref7.4.4PM2bEdge WrappingYesTXP-00037.4.3PM3Pass ThroughYesTXP-00047.4.4W1Wrapped StationYesTXP-00037.6.2W2Frame Fields for WrappingYesTXP-00037.6.2W3Frame Fields for UnwrapYesTXP-00037.5SH1Crossing Below Low LimitYesCCT-0001 to 3 and TXP-0001, 27.5SH2High Limit ValueYesCCT-0001 to 3 and TXP-0001, 27.5.1SH3Decrement FrequencyYesCCT-0001 to 3 and TXP-0001, 27.5.1SH4AccuracyYesCCT-0001 to 3 and TXP-0001, 27.6.1CC1Steering PurgeYesTXP-00037.6.1.1CC2Queue PurgeYesTXP-00037.6.1CC3Wrapping PurgeYesTXP-00037.6.2CC4Wrapping Field RequirementsYesTXP-00037.6.2CC5Unwrapping Field RequirementsYesTXP-00037.7.3TTL1TTL SettingYesCDT-00027.7.3TTL2TTL Base SettingYesCDT-00027.7.7.1FO1Single QueueYesTXP-0001FO2Dual Q PTQ – FIFO OrderYesTXP-0002FO3STQ FIFO OrderingYesRPR-0008FO4Dual Queue Cross OrderingYesRPR-0008Chapter 88.31Gb/s PHY Reconciliation SublayerYesGMII-0001 to 710Gb/s PHY Reconciliation SublayerYesXGMII-0001 to 7SONET/SDH Reconciliation SublayerYesSPI3-0001 to 7GFP Reconciliation SublayerNO8.2.3.3PHY LINK STATUS IndicationYes8.3.1.1PRS-1 Provides GMII FunctionYesGMII-0001 to 7PRS-10 Functional 1-7Matched Ringlet RatesYesGFP Framing ComplianceNoHDLC FramingNoHDLC Link ComplianceNoLAPS FramingNo9.2Basic Data framesYesCDT-00039.2Extended Data FrameYesCDT-00039.3Control FrameYesTPT-00059.4Fairness FrameYesRPR-0015, FCB-00109.5Idle FrameYesCCT-00048.48.4Chapter 9: Frame Format9.6.2,Fe ReservedYesRPR-00159.6.6,Parity ReservedYesRPR-001514www.xilinx.comWP233 (v1.0) October 19, 2005
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsTable 4:RPR MAC Compliance Matrix (Continued)SubclauseNameDetailsSupportTest Case Ref9.7.5,Res ReservedYesRPR-00159.5.2.4Idle PayloadYesCCT-000410.4.1Rate StatisticsYesFCB-000210.4.1Rate Statistics Maintenance DelayYesFCB-000210.4.1Chapter 10Policing 2.4Low Pass FilteringYesFCB-0003Aging IntervalYesFCB-000310.410.4.3Aggressive Rate ComputationYesFCB-000410.4.4Conservative Rate ComputationYesFCB-000510.4.5Rate AdvertisementYesFCB-000710.4.6Rate ReportYesFCB-000710.4.7Active Weights ComputationYesFCB-000810.4.8Single Choke Fairness FramesYesFCB-000910.4.8Multi ChokeFairness FramesYesFCB-000910.4.9FDD Frame TransmitYesFCB-001010.4.10FRTT ComputationYesFCB-001110.4.3Shaper-Based AdmissionYesFCB-000310.4.3Rate-Based AdmissionYesFCB-0003Chapter 1111.6.2SM1Receive Monitor State mcYesTPB 0001, TPB 000411.6.3SM2Topology ControlYesTPB 0005 to TPB 000911.6.4ParseTPframeYesTPB 0010 to TPB 001711.6.5ProtectionUpdateYesTPB 0018 to TPB 002011.6.6Topology ValidationYesTPV 0001 to TPV 000511.6.7TransmitTPframeYesTPT 0001 to TPT 000411.6.8TransmitTCframeYesTPT 0005 to TPT 000711.6.9ReceiveTPframeYesTPR 0001 to TPR 000311.6.10ReceiveTCframeYesTPR 000611.6.11TransmitATDframeYesTPT 0013 to TPT-001411.6.12ReceiveATDframeYesTPR 0007 to TPR 000811.6.13Secondary UpdateYesTPR 0009 to TPR 001311.6.14TimingLRTTframeYesTPR 0014, TPT 0009 toTPT 0012TP FrameYesTPR-0001- TPR-000311.3.137511.3.2TC FrameYesTPR-000611.3.3LRTT Request FrameYesTPR 0014 to TPR-0017 and TPT0009 to TPT-001211.3.4LRTT Response FrameYesTPR 0014 to TPR-0017 and TPT0009 to TPT-001211.3.4Tail Latency IN Field SettingYesTPR 0014 to TPR-0017 and TPT0009 to TPT-0012WP233 (v1.0) October 19, 2005www.xilinx.com15
RTable 4:White Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsRPR MAC Compliance Matrix (Continued)SubclauseDetailsSupportTest Case Ref11.3.4Tail Latency OUT Field SettingYesTPR 0014 to TPR-0017 and TPT0009 to TPT-001211.3.5ATD FrameYesTPR 000811.3.5ATT AdvertisingYesTPR-000811.3.5ATT Advertising, DefaultYesTPR-000811.3.5ATT Not IncludedYesTo be updated.11.3.5Type Dependent LengthYesTPR-0008Weight ATTYesTPR-000811.4.1Name37611.4.2Station Bandwidth ATTYesTPR-000811.4.2Reserved Bandwidth Within StationBandwidth ATTYesTPR-000811.4.2Excess Reserved Rate DefectYesTPR-000811.4.3Station Settings ATTYesA software function.11.4.4Station Name ATTYesA software function.11.4.5Station Management ATTYesTo be updated. It is a devicedriver function.11.4.5Managed EntityYesA software function.11.4.6Station Interface Index ATTYesTPR-000811.4.7Secondary MAC ATTYesTPR-000811.4.7First 2ndary MAC Q Address SettingYesTPR-000811.4.72nd 2ndary MAC Address SettingYesTPR-000811.4.8Organization Specific ATTYes11.1.6.3Protection for Relaxed Data FramesYesTPB-000811.1.6.3PP1-7Protection for Strict FramesYesTPB-0008, RXD-002711.1.6.1Steering ProtectionYesTPB-0008, 000911.1.6.2Wrapping ProtectionYesTPB-0008, 000911.2.3Revertive OperationYesTPB-0008, 000911.2.3Non-Revertive OperationTBDTPB-0008, 0009Failure of Transit PathYesTPB-0008, 0009Topology Discovery in Maximum SizeRingYesTPB-0010 to TPB-0014Persistent Topology InconsistencyYesTPB-0010 to TPB-0014ATD TimerYesTPT 001311.6.11ATD Transmission (ATD2,3)YesTPT 001311.6.11Claiming Ownership of ResourcesThrough ATTsYesTPR 0011, TPR 0018, 1911.6.11Handling Race Conditions in ATDYesTo be updated.11.6.12ATD ReceptionYesTPR 000711.6.12Illegal ATD DiscardsYesTPR 000711.6.5.211.6.811.6.6.111.2.311.6.14LRTT1LRTT Request ProcessingTPT 000911.6.14.4LRTT Response TimeYesTPT 000911.6.14.4No Late LRTT ResponseYesTPT 001611.6.14.4LRTT Re-MeasurementYesTPR 0015Organization Specific FramesYesOAM-0006Chapter 1212.3.316398www.xilinx.comWP233 (v1.0) October 19, 2005
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsTable 4:RPR MAC Compliance Matrix st Case RefPerformance MonitoringYesOAM-0010 - 0014OAM Transmit State m/cYesOAM-0003OAM Frame Receive stmcYesOAM- 0004ECHO Frame FormatsYesOAM 0001, 0002Flush Frame FormatsYesOAM-0005Organization Specific Frame FormatYesOAM-000612.4.1Echo Request/Response FormatsYesOAM-0001, 000212.4.1Echo Request/Response FormatsYesOAM-0001, 0002Echo Flush FormatsYesOAM-0005Echo Flush FormatsYesOAM-0005Organization Specific FormatsYesOAM-0006Organization Specific FormatsYesOAM-000612.6.1.2Scff ErrorsYesOAM-001012.6.1.3Errored lable TimeYesOAM-0013PM5YesOAM-0014SMEYes13.2LME PrimitivesYesLME 000113.2LME Initialization PrimitivesTBDLME 000212.6.1.2,3,4Chapter 1313.141013.2LME Initialization AttributesTBDLME 0002Administrative Status Down (LME4,LME5, LME6)TBDLME-0003 to 513.3.2Topology DiscoveryYes13.3.3Performance and 3.1SystemArchitectureUse CasesTo be added.Several different use cases can be explored. One use case is common for anIPDSLAM/GPON OLT in which multiple IP streams must be aggregated and sentthrough the ring. Another use case is an MSPP application where legacy TDM traffic ismixed with data traffic. These two use cases comprise the majority of applications.WP233 (v1.0) October 19, 2005www.xilinx.com17
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsFigure 11 shows the basic system architecture for 1G and/or 2.5G. This is a goodstarting point.Datapath Interface(Backplane Bus orSwitching Logic)Local or SytstemControl BlockOptionsControl Block Can Be Situated on theDatapath Itself(A Remotely Placed Control Unit)RPR MAC CoreFPGAGMIISPI 3.0PCSGFP/HDLCFramingSERDESSONETFramerSFPSERDESRPR MAC Driver(RPR Stack)FirmwareEither GMII or SPI 3.0 will be Presentin the SystemInterface Option is Selectable at the Timeof CompilationSPI 4.x is Optional, will be Added if ValidatedCore is Available10G Ethernet is Not ShownSEPWP233 11 091505Figure 11:System Architecture Baseline for 1G/2.5G RPR InterfaceNote that for the Sonet side, the framer could incorporate VCAT/LCAS to mix traffic.IPDSLAM/GPON OLTIPDSLAMs are rolling out from several vendors. GPON OLTs are starting to roll out aswell. The application is the same; distribute and aggregate a bunch of IP streams overGPON or DSL. This is the access story from most tier 1 service providers. RPR is anideal transport mechanism to distribute and aggregate this traffic. Figure 12 shows atrunk card implementation for this application.18www.xilinx.comWP233 (v1.0) October 19, 2005
RWhite Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAsSRAM / SDRAMSDRAMMemory Manager / ControllerTrafficMgmtSFPOC 48SonetMapper /FramerGFP-FSPI 3.0RPRMACVLANSwitching /Bridging802.3ADVirtualEthernetPortsRFC2684AAL 5SegADSLBondingUTOPIA2(32 ch)RFC2684 /EtherHdrAAL 5ReassADSLBondingUTOPIA2(32 ch)Memory Manager / ControllerHostPortSRAM / SDRAMRPR Driver,Framer DriverμP(PPC,MicroBlaseor ext.)SWProcessingWP233 12 091405Figure 12:IPDSLAM Trunk Card ArchitectureThe RPR MAC, SPI3.0 interface and RPR driver are packaged as a part of the RPRsolution. The rest is all IP blocks from other vendors. The traffic manager might not beneeded if the granularity of QoS on the RPR MAC is enough. A GPON OLT trunk cardwould look very similar except the ATM interfaces would all be gone. IP can godirectly to the OLT line cards.MSPP ApplicationThis application's main difference is that legacy TDM traffic must be preserved. Ablock diagram of a system is shown in Figure 13.ControlCardTD
R White Paper: IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAs Background Legacy communication systems are heavily deployed with ring topologies. DS1 and DS3s are often deployed in rings with ring switches. More recently, SONET/SDH is based on rings including the Bidirectional Line Switched Ring (BLSR) and the
