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Figure 4.6.(a) Schematic diagram of the contact structure. (b) Cross sectional TEMimage of the Al/SiN/n-GaAs contact . 55Figure 4.7.There exists an optimal insulator thickness for minimal contact resistance,which arises from the tradeoff between a reduced barrier and and anincreased tunneling resistance. . 56Figure 4.8.RC measurements of the Al/SiN/n-GaAs MIS shows the expected RCtradeoff with dielectric thickness. 57Figure 4.9.Back-to-back Al/SiN/n-GaAs diode measurement demonstrate the effectivemodulation of ΦB,eff by the SiN thickness. 58Figure 4.10.RC vs. tINS for different substrate dopings. . 59Figure 4.11. Simulation of the tunneling limited contact resistance of Al/SiN/n-GaAs bya fully self-consistent NEGF simulation . 60Figure 4.12. RC ratio of metal/SiN/GaAs MIS using different metals. . 61Figure 4.13. Equation and linear fitting used to calculate the ideality factor. . 62Figure 4.14. (a) Diode current measurement across temperature. (b) ΦB,eff extractionfrom the Arrhenius plot. (c) Equations. . 63Figure 4.15. (a) ΦB,eff is decreases with increasing SiN thickness. (b)The idealityfactors increases with SiN thickness . 64Figure 4.16. Effective barrier height vs. metal work function for Schottky diodes andMIS contacts. . 64Figure 4.17. Comparison of the RC vs. tINS tradeoff for SiN and Al2O3. . 66Figure 4.18. (a) RC vs. tINS tradeoff for different dielectrics (b) The tunneling barrierheight dependence on the conduction band offset. (c) Dielectric materialsaffect both the RSB and RT branches. 67Figure 4.19. The effect of different metals, dielectrics, and substrates on the tradeoffbetween RC and insulator thickness. . 68Figure 4.20. (a) MBE grown n-InGaAs substrate on InP. (b) RC tradeoff indicates thesuccessful reduction in the InGaAs barrier height. . 69Figure 4.21. Schematic view of the fabricated InGaAs MOSFET . 70Figure 4.22. (a) Circular TLM data. (b) TLM measurement results show similar RCtrends as from diodes. (c) RTOT vs. L plot from MOSFETs of differentiv

dimensions. (d) MOSCAP C-V from 2kHz to 1MHz . 71Figure 4.23. SiN MIS contact implemented on a surface channel enhancement modeInGaAs nMOSFET with L 10 μm. (a) ID-VG. (b) ID-VD . 72Figure 5.1.Experimentally measured Schottky barrier heights on n-GaAs for differentmetal work functions. . 75Figure 5.2.Distribution of the metal induced gap states. . 77Figure 5.3.(a) Illustration of the relation between S and ε . (b) The slopes show that asmaller S leads to a higher degree of pinning of EF to ECNL. . 78Figure 5.4.Illustration of the interface specific region. . 79Figure 5.5.Schematic band diagrams: (a) Schottky barrier with a pinned Fermi level,(b) Fermi level umpinning through MIGS reduction, (c) Fermi levelshifting through dipole formation at the interface . 80Figure 5.6.No reduction in p-InGaAs ΦB,eff, suggesting the Fermi level is shiftedtowards the conduction band, rather than depinned. . 82Figure 5.7.The roughly parallel shift in ΦB,eff independent of ΦM confirms thedielectric dipole induced shift of roughly 0.4 to 0.5eV. . 83Figure 5.8.The RC vs. TiO2 thickness tradeoff plot for Al/TiO2/n-GaAs MIS contactsappears to be independent of the surface passivations. . 84Figure 5.9.After removing the positive fixed charge in Al/Al2O3/n-GaAs MIS (a)there is no longer a reduced barrier height and (b) the current decreases. 86Figure 5.10. Al/Al2O3/n-GaAs RC vs. tINS comparing samples with ALD depositiontemperatures of 250 and 300oC. 87Figure 5.11. (a) As deposited Pt/HfO2/InGaAs MOSCAP C-Vs for different oxidethicknesses. (b) After annealing in FGA at 300oC for 15 min, the MIScontact resistance increased greatly. . 88Figure 5.12. Schematic band diagrams illustrating how the presence of electronicdipoles and fixed charge can affect ΦB,eff. . 89Figure 6.1.(a) Schematic of the investigated bilayer dielectrics. (b) Illustration of howthe high-κ/SiO2 dipoles affect the band alignments. (c) Extracted barrierheights for varying dielectric thicknesses show the Si Fermi level is tunedtowards the conduction and valence bands.iv(d) ID-VD of FinFETs

comparing the effect of MIS and the control contacts. . 94Figure 6.2.(a) C-V of MOSCAPs with and without high-κ GeO2. (b) Survey of high-κmaterials and their corresponding VFB shifts. (c) Illustration of theequalization of the oxygen areal density through oxygen transfer at theinterface and dipole formation. . 95Figure 6.3.(a) VFB shift of NiSi/A12O3/HfO2/SiO2/Si MOSCAPs. (b) VFB shift ofNiSi/HfO2/Y2O3/SiO2/Si MOSCAP. . 96Figure 6.4.MIS diode current of Al/TiO2/n-GaAs and bilyaer Al/Al2O3/TiO2/n-GaAswith a constant 13Å TiO2 thicknes . 99Figure 6.5.Al/Al2O3/TiO2/n-GaAs MIS diode current with a constant 7Å Al2O3thickness and varying TiO2 thickness. . 100Figure 6.6.Diode current of Al/HfO2/TiO2/n-GaAs with a constant 13Å TiO2 (30cy)thickness and varying HfO2 thickness. . 100Figure 6.7.Diode current of Al/ZrO2/TiO2/n-GaAs with a constant 13Å TiO2 (30cy)thickness and varying ZrO2 thickness. . 101Figure 6.8.Comparison of the maximum current in Al/Al2O3/TiO2/n-GaAs,Al/HfO2/TiO2/n-GaAs and Al/ZrO2/TiO2/n-GaAs bilayer MISt. . 101Figure 6.9.Schematic of RC vs. tINS illustrating the tradeoff. . 102Figure 6.10. Optimization of the TiO2 and Al2O3 thicknesses for minimum RC byholding on thickness constant and varying the other and vice versa. 102Figure 6.11. (a) RC vs. tINS for MIS contacts using TiO2, Al2O3, and TiO2 Al2O3.(b) MIS contacts with TiO2, HfO2, and TiO2 HfO2 dielectrics show thesame trends as TiO2 Al2O3. 103Figure 6.12. RC vs. tINS for MIS contacts using TiO2 HfO2, TiO2 ZrO2, and TiO2 Al2O3 bilayer dielectrics.These bilayer MIS contacts result in lower Rcthan their single dielectric MIS contact counterparts . 104Figure 6.13. Summary of minimum RC of single and bilayer MIS. . 105Figure 6.14. Summary of the effective barrier height of single and bilayer MIS. . 105Figure 6.15. Summary of minimum RC of single and bilayer MIS. . 106Figure 6.16. Comparison of gate leakage of Pt/TiO2/Ge MOSCAPs with and without anAl2O3 interlayer. . 107iv

Figure 6.17. Bilayer MIS diode current measured immediately, 3 days, 6 days, and 9days after fabrication, . 108Figure 6.18. (a) Current device structure. (b) Device structure needed to prevent TiO2degradation over time. . 109Figure 6.19. (a) Schematic of net dipole build up due to screening ability differences atthe interface. (b) Illustration of how the dipole magnitude changes with theelectronegativity of the dopant atom. . 110Figure 6.20. Effect of RTA annealing on the contact resistance of Al/dielectric/n-GaAssingle dielectric and bilayer MIS. 113Figure 6.21. Schematic of the transfer of oxygen from the higher σ to lower σ material,leaving behind a positively charged oxygen vacancy and adding anegatively charged ion on the other side to form the dipole. . 114Figure 6.22. Summary of the conduction band offsets and calculated σ ratios takenrelative to TiO2 for the investigated dielectrics. . 115iv

Chapter 1Introduction1.1 MotivationThe silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) hasbeen the most important building block of Integrated Circuits (ICs) since its invention inthe 1960s. It is used as elemental units to build both switches for digital logic andamplifiers for analog applications. To continuously improve the performance andcomplexity of ICs, the semiconductor industry has been faithfully following Moore’sLaw [1], which states that the number of transistors doubles every two years (Figure1.1a). As a result, although the basic device structure and functionality has remained thesame, the physical dimensions have been continuously shrinking for the last 40 years.This MOSFET scaling has not only technological benefits, but also economical benefitsof reducing cost per transistor through increased device density. However, Dennard’sidea of “classical scaling” [2] through simple physical scaling of dimensions ended afterthe 130 nm technology node as increasing leakage currents were causing an unacceptableexponential increase in the off-state static power consumption (Figure 1.1b). With theon-current scaling linearly at a much slower rate than the off-state current, significantchanges were required to enhance the on-current and minimize off-current.As a result, tremendous research and developments efforts were put forth tomaintain the desired technological advancements. New materials and device structureswere introduced to boost the performance and to make up for the loss of classical and1

(a)(b)Micron10110010-110-2Figure 1.1. (a) Illustrration of Mooore’s Law whhere the nummber of transiistors doublessevery twoo years and thhe dimensionns scale to immprove performmance and reeduce the costtper transiistor. (Adapteed from Intel) (b) The off-state leakage or power is exponentiallyyincreasingg as we scale and is approaaching the acttive power. (AAdapted from Intel)gate oxide scaling (Figurre 1.2). Straiined silicon was introduuced in the 909 nm technoologynode to enhannce the carriier mobilitiees, high-k/mmetal gate in the 45 nm nodento miniimizethhe gate leakkage, and FinFETs in thhe 22 nm noode to reducce the shortt channel efffects.HHowever,as silicon begiins to reach its fundameental limits, even greaterr hurdles neeed tobe overcome where the useu of more novelnmateriials and device structurees may be neeededtoo continue CMOSCscaling. High mobility chhannel mateerials such asa Ge and III-Vcoompounds offeroa potenttial solution to meet the power and performancepe specificatioons offuuture CMOSS nodes [3]. In this theesis, we focuus on III-V semiconducctor FET deevicestaargeted for beyondb15 nmm digital loggic applicatioons.III-V semiconductors are commpounds commposed of grroup III elemments (In, Gaa, Al,ettc.) and grouup V elemennts (As, Sb, N, P, etc.) that in geneeral have siggnificantly higherhellectron and hole mobilities than silicon. Higgher mobilitties and injection velocitiesiddeally translate to betterr MOSFET performancee, where theese mobilitiees can be fuurtherennhanced thrrough physiccally straininng the mateerials. The excellentetrannsport propeertiescooupled with smaller bannd gaps givee III-V semiiconductors the advantaage of high speeds2

and low power operation. However, for III-V FETs to become a viable technology thereManufacturingLG 35 nmDevelopment30 nmResearch10 nm20 nm5 nmNanowireStrainedSiliconMetal GateCarbonNanotube FETHigh-kSi SubstrateFinFETHK/MGSource: IntelBeyond Si CMOSFigure 1.2. TEM images of MOSFET scaling over the years with technologicaladvances labeled. (Adapted from Intel)are several challenges that need to be overcome. These include (1) finding an optimal,reliable high-k gate dielectric, (2) a cost effective integration of III-V materials on Si, and(3) a scalable low resistance ohmic contact.Ohmic contact formation on III-V semiconductors is fairly difficult because thereis strong metal/III-V Fermi level pinning that results in high Schottky barrier heights. Inmaterials with large bandgaps such as GaAs (1.42eV), the pinned barrier can be fairlylarge, ranging from 0.7 to 1.0eV [4]. Without the silicidation technology available to Si,III-V materials traditionally rely on multi-layered alloyed structures to form ohmiccontacts, such as Au/Ge/Ni in the case of GaAs [5]. However, these source/drain (S/D)contact materials can then diffuse up to hundreds of nanometers during alloying whichseverely limits the scalability of III-V logic technology [6]. Recently there have beenmany demonstrations of III-V FET/HEMTs with excellent performance [7-13], but mostof these demonstrations are on devices with micron scale S/D spacings despite nanometerscale gate lengths (Figure 1.3). To reduce the device footprint in line with the expecteddevice density improvement, it becomes necessary to develop scalable non-alloyedcontacts.3

Figure 1.3. Illustration of a device with a 50nm gate length but a device pitch ofmore than 2μm. Figure from Ref#[14].Another issue with large gate to S/D spacing is the increase in the series resistanceand therefore the delay, which counteracts the benefit of the excellent III-V transportproperties. Figure 1.4 illustrat

nanoscale iii-v compound semiconductor field effect transistors a dissertation submitted to the department of electrical engineering and the committee on graduate studies of stanford university in partial fulfillment of the requirements for the degree of doctor of philosophy jenny ruey-chen hu december 2011