Bidirectional Three-Level DC-DC Converters: Sum-Difference .

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Bidirectional Three-Level DC-DC Converters:Sum-Difference Modeling and ControlMichael Eull and Matthias PreindlDepartment of Electrical Engineering, Columbia University in the City of New Yorkmatthias.preindl@columbia.eduAbstract—This paper proposes a modeling and control approach for the three-level DC-DC converter. The converter isdescribed in a sum and difference (Σ ) framework. It is shownthat the formulation is useful to model the inverter and derivedesign-specific equations. The Σ component is responsible for theinductor current, i.e. the power flow, and the component isused to balance (or unbalance) the DC-link capacitor voltages.It is shown that there are cross-coupling terms between the Σand axes that can be compensated. The proposed model isvalidated using high fidelity simulations with a proportionalintegral controller. Two- and three-level converter operation isshown and it is proven that the passive components can bereduced by 50% to 75% using three-level operation withoutaffecting the control performance. The control is verified byintroducing load current and DC voltage steps.I. I NTRODUCTIONBidirectional non-isolating DC-DC converters are a keytechnology for electrified transportation systems. They areparticularly relevant for vehicles with more-electric drivetrains[1]–[3]. DC-DC converters are used to interface energy storagesystems in electric vehicles (EV) and plug-in hybrid electricvehicles (HEV) and energy transformation units in fuel-cellvehicles [4]–[6]. The energy necessary for xEV traction can beprovided by one or more electrical energy sources or storagemediums. Non-isolating DC-DC converters are necessary tointerface different voltage levels and to control the powerflow [7], [8]. An example are EVs with hybrid energy storagesystems [9], [10], where a battery pack stores the energy fora suitable driving range and an ultracapacitor pack providespeak power and handles micro-cycling [8].Numerous converters have been proposed and comparedin literature [7], [11]–[13]. DC-DC converters for xEV aretypically benchmarked with respect to efficiency. xEVs requirea high efficiency over a wide range of operating points thatare defined by city and highway driving cycles. A promisingsolution is the three-level DC-DC converter [14], [15] that iscapable of operating at high efficiency over wide load and highvoltage transformation ranges. In particular, this converter hasbeen shown to be highly competitive when compared to thetwo-level and two-level inverterleaved converters [16].This paper proposes a novel modeling and control approach for the three-level DC-DC converter. The converteris described in a sum and difference (Σ ) framework. It isshown that the formulation is useful to model the inverter andderive design specific equations. Design equations are givenfor balanced operation and can be easily extended to unbal-978-1-5090-3953-1/ 31.00 2017 IEEEiLS1L IbCb vbic1C1 v1S2 vsvdS3C2Id v2S4 ic2Fig. 1: Three-level DC-DC converter.anced operation. The results are confirmed by simulation. Theconverter is operated in both two- and three-level operation.The latter introduces vertical interleaving to reduce passivecomponents. It is proven that the passive components can bereduced by 50% to 75% using three-level operation. The sameratio holds when comparing the 2L DC-DC (conventionalbuck-boost converter) to the 3L DC-DC converter.The Σ framework is further used for control. It canbe used in a fashion similar to the dq framework that iswidely employed in motor drives [17]. The Σ component isresponsible for current control, i.e. the power flow, whereas the system is used to control the voltage sharing of the DClink capacitors. It is shown that there are cross-coupling termsbetween the Σ and axes and that they can be compensated.Compensation is optional and can be taken care of by asufficiently fast feedback controller. The control is verified byintroducing load current and DC voltage steps in high fidelitysimulations.II. A NALYSISThe bidirectional three-level boost converter has four usefulswitching states. One of the upper two switches (S1 and S2 )needs to be off to avoid short-circuiting the voltage v1 (t).TABLE I: Switching states, capacitor currents and outputvoltages for the three-level 4s(t)[ic1 ,ic2 ]0vs (t)offoffonon[0,0]0[1,0]0[0,1]0[0,0]0[ iL ,0]0[0, iL ]0[ iL , iL ]00v1v2v1 v2[1,1]0

Likewise, one of the lower two switches (S3 and S4 ) needsto be off to avoid short-circuiting the voltage v2 (t). Turningboth S1 and S2 (or S3 and S4 ) off yields a voltage, vs (t), thatdepends on the sign of the current and is ignored in this text.The resulting useful switching states are shown in Table I andFig. 2.To simplify the modeling, we introduce the binary switchingstate s(t) [s1 (t),s2 (t)] {0,1}2 and capacitor voltagev12 (t) [v1 (t),v2 (t)]0 R2 , where vd (t) 10 v12 (t) v1 (t) v2 (t) R . Hence, the voltage that is applied tothe inductor is vs (t) v12 (t)0 s(t) R . In practice, DC-DCconverters are typically designed for Pulse Width Modulation(PWM). PWM translates a duty cycle d [d1 ,d2 ]0 [0,1]2into a switching sequence with time averageZ kTsw Tsw1s(t) dt,(1)d Tsw kTsw(a) s [0,0]0(c) s [0,1]0(d) s [1,1]0Fig. 2: Conduction paths as a function of the switching states(t).Adding the dynamic equation of the capacitor Cb , we obtainthe full dynamics of the system in scalar notation:TsTs(vd dΣ v d ) vb ,2LLTs v v iL d ,C2TsTs vd vd iL dΣ Id ,CCTsTsiL Ib ;vb vb CbCbi L iL where Tsw is the switching period. Similarly, the model canbe rewritten using average modeling (neglecting second ordercomponents)0vs v12d v1 d1 v2 d2 .(b) s [1,0]0(2)(8a)(8b)(8c)(8d)Furthermore, we introduce the sum and difference notationdΣ [dΣ ,d ]0 Td and vΣ [vΣ ,v ]0 Tv12 , where 1 1T (3)1 1or, in matrix form,and vΣ vd . The updated notation yields 0 vs T 1 vΣ T 1 dΣ 11 0 vΣ dΣ (vd dΣ v d ) ,22where x [iL ,v ,vd ,vb ]0 is the state vector, u dΣ is theinput and e is the exogenous input. Their parameters are Ts Ts T(4a)(4b)and the (discrete-time) dynamic equation of the inductorcurrentTsTsvs vbLLTsTs iL (vd dΣ v d ) vb ,2LLi L iL (5a)(5b)where the sampling period Ts Tsw for simplicity and . denotes entities of the (discrete) sampling time instant t Ts .The voltages on capacitors C1 and C2 vary as a function ofthe inductor current and duty cycle, per v12TsTs v12 iL d Id ,CCx Ax B(x)u e,A 1 000 100 01Ts00Cb2L vdsL001 , B(x) 0 TsC iL02L v TsC iL00(9)00 ,e 2TsC Id TsC b Ib .The system (9) has a constant state parameter matrix and isaffine in the input with a state-dependent parameter matrix.The state-space system (8) defines the following controlproblems that need to be addressed to operate the three-levelDC-DC converter (6)where we assume C1 C2 C for simplicity and Id is theconstant DC current. This equation states that d1 0 andd2 0 discharges the capacitors C1 and C2 with current iL ,respectively. The duty cycles d1 0 and d2 0 bypass iL anddo not affect the capacitor voltage. The equation is rewrittenusing the sum and difference notation as 0Ts2Ts vΣ vΣ iL dΣ Id ,0 .(7)CC574 Power flow: the converter transfers the power p vb iL .Controlling the power translates into controlling iL sincevb is approximately constant (by design or control).Symmetric operation: Converters are typically implemented with one type of semiconductor and capacitor.To minimize component stresses, the capacitor voltagesshould be symmetrical, which can be achieved by controlling v to zero.Voltage stabilization: Either vb or v12 can be controlledvia the power flow through the converter. The othervoltage needs to be stabilized via the exogenous input(Ib or Ic ) since the converter cannot store significantamounts of energy. Stabilization can be achieved throughconnection to a DC bus or energy storage system (batteryor ultracapacitor).

120.5120119.54054003952010020(a) No interleaving, d1 0.3.120.5120119.5100202200198405400395pwmvs [V]02010t [us ]020(b) Interleaving, d1 0.3.280.5280279.50101010101020010t [us ]4002000iL [A]iL [A]ic [A]020100020100502020605040ic [A]pwmvs [V]002010t [us ]10605040105020200vc [V]202200198d0020010.50202200198vd [V]2010100vb [V]vb [V]0040020004054003952020vb [V]1020vc [V]0502010vb [V]vd [V]40540039510605040cvc [V]20220019820010.50vd [V]pwmsv [V]104002000iL [A]00020ic [A]5010v [V]605040010.50v [V]pwmiL [A]4002000ic [A]vs [V]10.5020(c) No interleaving, d1 t [us ]20(d) Interleaving, d1 0.7.Fig. 3: High fidelity simulations, with and without interleaving, for C1 C2 Cb 30µF, L 47µH and fsw 100kHz. iL, vd [pu]0.30.20.1000.20.40.60.8100.20.40.6d d [pu]0.81 vb [pu]0.040.030.020.01012Fig. 4: Normalized current and voltage ripples. Continuousline: analytic functions (12), (13), (15), (16), (18) and (19);markers: current ( ) and voltage ( ) ripples obtained fromhigh fidelity simulation with C1 C2 Cb 30µF, L 47µH and fsw 100kHz.III. M ODULATIONThe upper bridge (switches S1 and S2 ) is actuated bythe duty cycle d1 and the lower bridge (S3 and S4 ) by d2using dedicated PWM modules. Both bridges can be operatedindependently from one another and two modulation strategiesare analyzed: two-level (2L) and three-level (3L) switching.The PWM carrier signals of the upper and lower bridge are inphase for 2L switching and phase shifted by 180 (Tsw /2)in 3L switching. Three-level switching can be interpretedas a vertical interleaving of the two bridges. Interleavingis generally considered to reduce current (voltage) ripplescompared to 2L switching. An example is shown in Fig.3.The switching ripples are analyzed in steady state condi tions. Substituting i L iL and v v in (28) yields vs vb and i 0, i.e. d 0, and d1 d2 dΣ /2 vb /vd .We also assume symmetric operation, where v 0 andv1 v2 vd /2. This operation yields symmetric voltageand current stresses on the upper and lower bridge and it canbe shown that it yields minimum ripples. In these conditions,it can be shown that the (constant) input/output currents areIc d1 iL and Ib iL .Both 2L and 3L switching yield a characteristic switchingpattern in the steady state that can be observed in Fig. 3. Twolevel switching only applies the switching states s(t) [0,0]0and s(t) [1,1]0 such that vs (t) switches between two voltagelevels: 0V and vd . In contrast, 3L switching applies all fourswitching states and vs (t) {0V ,vd /2,vd }. Dependent on theduty cycle, vs switches between 0V and vd /2 or vd /2 and vd .In addition, 3L switching effectively doubles the switchingfrequency for the passive components.To quantify the effects of switching, we formally definethe switching ripple as the peak-to-peak amplitude over Tswin steady state conditions. The switching ripple of inductorcurrent is defined asîL max iL (t) min iL (t) t [kTsw ,(k 1)Tsw ], (10)and the switching ripple of vs and vb are defined analogously.Switching ripples are calculated using the discrete versionof the characteristic inductor and capacitor equations. Theinductor current ripple results from575LîLT̂ v̂L ,(11)

where the voltage v̂L is assumed to be approximately constantand applied for the period T̂ . For 2L switching, the normalizedcurrent ripple isLîL,2L (d1 ) îL d1 (1 d1 )(12)Tsw vdwhen considering the off period where v̂L vb d1 vd isapplied for T̂ (1 d1 )Tsw . With interleaving, the currentripple depends on the value of d1 as follows:( 0.5 d1 d1 ,if 0 d1 0.5;îL,3L (d1 ) (13) 0.5 d1 (1 d1 ), if 0.5 d1 1.For d1 0.5 the voltage v̂L d1 vd is applied during the offinterval 0.5 d1 Tsw ; for d1 0.5, the voltage v̂L vd vb (1 d1 )vd is applied during the on interval 0.5 d1 Tsw .The vd voltage ripple is computed similar to îL . Thetreatment is based on the equationC v̂d îd ,2 T̂(14)where v̂d is the voltage ripple, îd is the capacitor current that isassumed to be approximately constant over the period T̂ thatit is applied, and C/2 is the resulting capacitance of the seriesconnected C1 and C2 . Without interleaving, the normalizedvoltage ripple isCv̄ˆd,2L (d1 ) v̂d d1 (1 d1 )(15)2Tsw ILRwhen considering the off period where îd Ib d1 ILR isapplied for T̂ (1 d1 )Tsw . The ripple is computed using therated (average) inductor current ILR , which yields the worstcase ripple. With interleaving, the voltage ripple is( 0.5 d1 d1 ,if 0 d1 0.5;v̄ˆd,3L (d1 ) (16) 0.5 d1 (1 d1 ), if 0.5 d1 1.For d1 0.5 the current îc Ib d1 ILR is applied duringthe off interval 0.5 d1 Tsw ; for d1 0.5, the current îc ILR Ib (1 d1 )ILR is applied during the on interval 0.5 d1 Ts .The computation of thevoltage ripple of vb is based on theassumption that the inductor current ripple circulates in thecapacitor. The charge, which varies with vd , is obtained byintegrating the triangular inductor current ripple in the positivehalf-period and is calculated as1 îLQ̂b Cb v̂b T̂ ,2 2where T̂ Tsw /2. With interleaving, T̂ Tsw /4 and weobtainîL,3L (d1 ).16IV. D ESIGNThe switching ripples of the presented boost converterdepend on the modulation technique. Three-level switchingsignificantly reduces the current and voltage switching ripplescompared to 2L switching. Hence, 3L switching can be usedto reduce the passive components. This section presents designequations for 2L and 3L switching.The maximum normalized ripple is obtained by derivingthe analytic expression and setting it to zero. Using the 2Linductor current ripple as an example, we have d ˆīL,2L (d1 ) 1 2d1 0 d1,2Lmax 0.5. (20)d d1In the same fashion, d1,3Lmax 0.25 for 3L switching. Thesame duty cycles are obtained for the maximum voltageripples. The maximum 2L normalized ripples are obtained bysubstituting the duty cycles in (12), (15) and (18):ˆīˆd,2Lmax 250 · 10 3 ,L,2Lmax v̄v̄ˆb,2Lmax 31.2 · 10 3 .(19)(21a)(21b)The maximum 3L normalized ripples are obtained by substituting the duty cycles in (13), (16) and (19):ˆīˆd,3Lmax 62.5 10 3 ,L,3Lmax v̄v̄ˆb,3Lmax 3.9 10 3 .(22a)(22b)Once the maximum normalized ripples are known, the designequations result directly from (12), (15) and (18). Transforming these equations, we obtainvdfsw îLmax2ILRC1 C2 C v̄ˆd,maxfsw v̂dmaxvdCb v̄ˆb,max 2fsw Lv̂bmaxL ˆīL,max(17)where T̂ is the duration of the half-period. Without interleaving, we obtain the normalized voltage rippleLCb11v̄ˆb,2L (d1 ) 2v̂b îL,2L (d1 ) d1 (1 d1 ), (18)Tsw vd88v̄ˆb,3L (d1 ) The normalized switching ripple is provided by (12), (13),(15), (16), (18) and (19) and shown in Fig. 4 as continuous lines. The analytic equations are validated using ahigh fidelity MATLAB/Simulink model with Simscape/SPICEcomponents applying (10) to the steady state waveforms ford 0.1,0.2, . . . ,0.9. The results are shown in Fig. 4 as markerswith current being circles ( ) and voltages crosses ( ).(23a)(23b)(23c)where fsw 1/Tsw is the switching frequency. The normalized ripples ˆīL,max , v̄ˆd,max and v̄ˆb,max are either the normalized2L switching ripples specified in (21) or the normalized 3Lswitching ripples specified in (22). The maximum peak-topeak current ripple, îL,max is often chosen as 40% of ILR . Themaximum peak-to-peak voltage ripples v̂d,max and v̂b,max aretypically specified design requirements.The required inductance and capacitance values can be putinto relation for a 2L and 3L design that use the same voltages(vd and vb ), current (ILR ), inductor current ripple (îL,max )576

YL YL ELEL 34 0.5LI 20.5L I 2 34 LL ,pwmvs [V]iL [A]706050ic [A]800400050201040440039680280079820120019920100vc [V]20vd [V]10010.50vb [V]vc [V]4014003992010002010t [us ]20010200102001020010200102001020010t [us ]20(a) 2L.(b) 3L.Fig. 5: Reference design (Table II) validation for worst-caseduty cycles: d 0.5 for 2L and d 0.25 for 3L.FB and FF ControlrLDuty Cycle Calculationvs - PIiLvb - PIvΔiΔ vΔ/2-vd/2* dΣΣΔd1.5**rΔ(27)-1iL* dΔ12d2Fig. 6: Control block diagram with feedback (FB) and feedforward (FF) control and duty cycle calculation. The compensation of v d /2 (grey blocks) can be typically omitted.be analyzed using common SISO tools, such as Bode plots.A simple control approach is obtained by assuming that theDC voltages, vd and vb , are effectively constant with respect tosampling instants (controlled externally or due to a connectedenergy storage system). This assumption can be relaxed suchthat only one voltage is constant using a(n) (outer) voltagecontrol loop. Ignoring (8c) and (8d), the state-space model isTsTsvs vb ,LLTs v v i ,C80280079820100V. C ONTROLi L iL 0404400396(26)where YC and EC are the capacitor volume and energy,respectively. Since the inductor (capacitor) works with thesame current (voltage), the volume ratio can be computedbased on the parameter values. Therefore, the inductor Lvolume can be reduced by a factor of about 2.8 using 3Lswitching compared to 2L switching. Similarly, the volume ofC and Cb can be reduced by a factor of 4 and 2, respectively.A 2L switching-based converter is compared to a (verticallyinterleaved) 3L switching-based converter with a referencedesign for each case. The design specifications and resultsare shown in Table II.100 34where YL and EL are the inductor volume and energy,respectively. The variables with superscript . belong to areference device using the same technology. The capacitorvolume scales approximately according toCYCEC0.5CV 2 YCEC0.5C V 2C5000(25)Hence, 2L switching requires 4 times the inductance L andcapacitance C compared to 3L switching. Although the inductance current ripple is the same, 3L switching requires halfthe capacitance Cb since the frequency of the current ripple is2fsw compared to just fsw for 2L switching.The impact of the filter parameter on volume can beestimated using scaling laws [18]. The inductor volume scalesapproximately according to 706050vd [V]1Cb,3Lv̄ˆb,3Lmax ˆīL,2Lmax . Cb,2L2v̄ˆb2L,max ˆīL3L,maxiL [A]and the capacitance Cb ratio is8004000ic [A]vs [V](24)10.50vb [V]ˆīC3LL3L1v̄ˆd,3LmaxL,3Lmax ˆˆL2LC2L4v̄d2L,maxīL,2Lmaxpwmand switching frequency (fsw ). The inductance L ratio andcapacitance C ratio is(28a)(28b)where vs is used to steer iL and i iL d steers v . Thedynamic equations are independent from one another and can577TABLE II: Two- and three-level converter design.Design SpecificationVoltage range vdVoltage range vbRated current ILRRipple amplitude v̂dmaxRipple amplitude v̂bmaxRipple amplitude îLmaxSwitching frequency fsw400V . . . 800V200V . . . 400V60A1%vdmin 4V1%vbmin 2V40%ILR 24A100kHzPassive Design2LInductance LCapacitance CCapacitance CbInductance ratio L3L /L2LCapacitor ratio C3L /C2LCapacitor ratio Cb3L /Cb2L83.3µH stimated Volume ReductionInductor volume ratio YL3L /YL2LCapacitor volume ratio YC3L /YC2LCapacitor volume ratio YCb3L /YCb2L3L35.4%25.0%50.0%

rΔ10vS , t [ms ]10(a) With compensation ofv d .2It is noted that the term iL can be positive, negative orzero. If iL 0, v is constant and not controllable. Hence,the computation of d in (30)–or, (31)–has to be protectedagainst division by zero. The control is shown in Fig. 7 usingsynchronous sampling.rLrΔ0510051005100510051005t [ms ]10VI. C ONCLUSIONSThis paper presented a Σ formulation of the three-levelDC-DC converter. Three-level operation is shown to reduceswitching ripples by 50% to 75%. Alternatively, the passivecomponents can be reduced by the same amount to achieve arequired switching ripple under the same operating conditions.The control can also be implemented in this framework andhas been demonstrated with a proportional-integral controller.10d [-]d [-]iL [A]vc [V]0500-50500-50d [-]1010.50500-50iL [A]d [-]vS , iΔ0500-50r [.]rLvc [V]r [.]500-50R EFERENCES(b) Without compensation.Fig. 7: Control evaluation for C1 C2 Cb 30µF, L 47µH, fsw 100kHz, with inductor current reference rL anddifference voltage reference r .The discrete-time transfer functions areiLTs 1v Ts 1tf 1 (z) ; tf 2 (z) . (29)vsL z 1i C z 1Power electronic systems are typically controlled usingproportional-integral (PI) feedback (FB) control thanks to itssimplicity of design and implementation. The PI controllersissue a vs and i value. The integral action is used to avoidcontrol biases, for example, due to actuation uncertainties(interlock times and on-voltage drop). However, the effectof vb is large and may yield unacceptable transients, e.g. atstartup. Hence, a feedforward term is added that compensatesthe effect of vb as shown in the block diagram in Fig. 6.The resulting control inputs vs vb and i cannot be actuated directly by PWM to the plant and need to be transformedinto duty cycles. In the Σ framework, we havedΣ vs vb v d /2,vd /2d i .iL(30)The resulting scheme (with grey blocks) is shown in Fig. 6.However, the term v is typically controlled to zero to ensuresymmetric operation (equivalent voltage stress and losses onC1 , C2 and the switches, etc.). If v 0, the effect of v d /2is small and the computation can be simplified todΣ vs vb,vd /2d i .iL(31)Hence, the grey blocks in the block diagram in Fig. 6 cantypically be omitted. To apply the duty cycles with PWM tothe plant, dΣ is transformed into d12 T 1 dΣ ; or,d1 dΣ d ,2d2 dΣ d .2(32)[1] I. Aharon and A. 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mediums. Non-isolating DC-DC converters are necessary to interface different voltage levels and to control the power flow [7], [8]. An example are EVs with hybrid energy storage systems [9], [10], where a battery pack stores the energy for a suitable driving range and an ultracapacito