WIXLIB

“Making of a Chip”Illustrations22nm 3D/Trigate Transistors – VersionJanuary 20121Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

The illustrations on the following foils are lowresolution images that visually support theexplanations of the individual steps.For publishing purposes there are highresolution JPEG files posted to the Intel ionally same resolution (uncompressed)images are available as well. Please requestthem from markus.weingartner@intel.com2Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

Sand / IngotSandSilicon is the second most abundantelement in the earth's crust. Commonsand has a high percentage of silicon.Silicon – the starting material forcomputer chips – is a semiconductor,meaning that it can be readily turnedinto an excellent conductor or aninsulator of electricity, by theintroduction of minor amounts ofimpurities.3Melted Silicon –scale: wafer level ( 300mm / 12 inch)In order to be used for computer chips,silicon must be purified so there is lessthan one alien atom per billion. It is pulledfrom a melted state to form a solid whichis a single, continuous and unbrokencrystal lattice in the shape of a cylinder,known as an ingot.Monocrystalline Silicon Ingot –scale: wafer level ( 300mm / 12 inch)The ingot has a diameter of 300mm andweighs about 100 kg.Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

Ingot / WaferIngot Slicing –scale: wafer level ( 300mm / 12 inch)The ingot is cut into individual silicon discscalled wafers. Each wafer has a diameter of300mm and is about 1 mm thick.4Wafer –scale: wafer level ( 300mm / 12 inch)The wafers are polished until they have flawless,mirror-smooth surfaces. Intel buys manufacturingready wafers from its suppliers. Wafer sizes haveincreased over time, resulting in decreased costs perchip. when Intel began making chips, wafers were only50mm in diameter. Today they are 300mm, and theindustry has a plan to advance to 450mm.Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

Fabrication of chips on a wafer consists ofhundreds of precisely controlled steps whichresult in a series of patterned layers of variousmaterials one on top of another.What follows is a sample of the most importantsteps in this complex process.5Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

PhotolithographyApplying Photoresist –scale: wafer level ( 300mm / 12 inch)Photolithography is the process by whicha specific pattern is imprinted on thewafer. It starts with the application of aliquid known as photoresist, which isevenly poured onto the wafer while itspins. It gets its name from the fact thatit is sensitive to certain frequencies oflight (“photo”) and is resistant to certainchemicals that will be used later toremove portions of a layer of material(“resist”).6Exposure –scale: wafer level ( 300mm / 12 inch)The photoresist is hardened, and portions of it areexposed to ultraviolet (UV) light, making it soluble.The exposure is done using masks that act likestencils, so only a specific pattern of photoresistbecomes soluble. The mask has an image of thepattern that needs to go on the wafer; it is opticallyreduced by a lens, and the exposure tool steps andrepeats across the wafer to form the same image alarge number of times.Resist Development–scale: wafer level ( 300mm / 12 inch)The soluble photoresist is removed by achemical process, leaving a photoresistpattern determined by what was on themask.Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

Ion ImplantationIon Implantation–scale: wafer level ( 300mm / 12 inch)The wafer with patterned photoresist isbombarded with a beam of ions (positively ornegatively charged atoms) which becomeembedded beneath the surface in the regions notcovered by photoresist. This process is calleddoping, because impurities are introduced intothe silicon. This alters the conductive propertiesof the silicon (making it conductive or insulating,depending on the type of ion used) in selectedlocations. Here we show the creation of wells,which are regions within which transistors will beformed.7Removing Photoresist–scale: wafer level ( 300mm / 12 inch)After ion implantation, the photoresist isremoved and the resulting wafer has apattern of doped regions in whichtransistors will be formed.Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.Begin Transistor Formation–scale: transistor level ( 50-200nm)Here we zoom into a tiny part of thewafer, where a single transistor will beformed. The green region representsdoped silicon. Today’s wafers can havehundreds of billions of such regionswhich will house transistors.

EtchingEtch–scale: transistor level ( 50-200nm)In order to create a fin for a tri-gatetransistor, a pattern of material calleda hard mask (blue) is applied using thephotolithography process justdescribed. Then a chemical is appliedto etch away unwanted silicon, leavingbehind a fin with a layer of hard maskon top.8Removing Photoresist –scale: transistor level ( 50-200nm)The hard mask is chemically removed, leaving a tall,thin silicon fin which will contain the channel of atransistor.Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

Temporary Gate FormationSilicon Dioxide Gate Dielectric–scale: transistor level ( 50-200nm)Using a photolithography step,portions of the transistor are coveredwith photoresist and a thin silicondioxide layer (red) is created byinserting the wafer in an oxygen-filledtube-furnace. This becomes atemporary gate dielectric.9Polysilicon Gate Electrode–scale: transistor level ( 50-200nm)Again using a photolithography step, atemporary layer of polycrystalline silicon(yellow) is created. This becomes atemporary gate electrode.Insulator–scale: transistor level ( 50-200nm)In another oxidation step, a silicon dioxidelayer is created over the entire wafer(red/transparent layer) to insulate thistransistor from other elements.Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

Intel uses a “gate last” (also known as“replacement metal gate”) technique forcreating transistor metal gates. This is done inorder to avoid transistor stability problemswhich otherwise might arise as a result of somesubsequent high temperature process steps.10Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

“Gate-Last” High-k/Metal Gate FormationRemoval of Sacrificial Gate–scale: transistor level ( 50-200nm)Using a masking step, the temporary(sacrificial) gate electrode and gatedielectric are etched away. The actualgate will now be formed; because thefirst gate was removed, this procedureis known as “gate last”.11Applying High-k Dielectric –scale: transistor level ( 50-200nm)Individual molecular layers are applied to thesurface of the wafer in a process called “atomiclayer deposition”. The yellow layers shownhere represent two of these. Using aphotolithography step, the high-k material isetched away from the undesired areas such asabove the transparent silicon dioxide.Metal Gate–scale: transistor level ( 50-200nm)A metal gate electrode (blue) is formedover the wafer and, using a lithographystep, removed from regions other thanwhere the gate electrode is desired. Thecombination of this and the high-k material(thin yellow layer) gives the transistormuch better performance and reducedleakage than would be possible with atraditional silicon dioxide/polysilicon gate.Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

Metal DepositionReady Transistor –scale: transistor level ( 50-200nm)This transistor is close to being finished.Three holes have been etched into theinsulation layer (red color) above thetransistor. These three holes will befilled with copper or other materialwhich will make up the connections toother transistors.12Electroplating –scale: transistor level ( 50-200nm)The wafers are put into a copper sulphatesolution at this stage. The copper ions aredeposited onto the transistor thru aprocess called electroplating. The copperions travel from the positive terminal(anode) to the negative terminal (cathode)which is represented by the wafer.After Electroplating –scale: transistor level ( 50-200nm)On the wafer surface the copper ionssettle as a thin layer of copper.Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

Metal LayersPolishing –scale: transistor level ( 50-200nm)The excess material is mechanicallypolished away to reveal a specificpattern of copper.13Metal Layers – scale: transistor level (six transistors combined 500nm)Multiple metal layers are created to interconnect (think: wires) all the transistors onthe chip in a specific configuration. How these connections have to be “wired” isdetermined by the architecture and design teams that develop the functionality ofthe respective processor (e.g. 2nd Generation Intel Core i5 Processor). Whilecomputer chips look extremely flat, they may actually have over 30 layers to formcomplex circuitry. A magnified view of a chip will show an intricate network ofcircuit lines and transistors that look like a futuristic, multi-layered highway system.Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.

After all the interconnect layers are formed, anarray of solder bumps is put on each die. Theseare the electrical connections with which thechip will communicate with the outside world,through the package in which it is later inserted.(these bumps are not shown in the illustrations)When wafer processing is complete, the wafersare transferred from the fab to an assembly/testfacility.There, the individual die are tested while still onthe wafer, then separated, and the ones thatpass are packaged. Finally, a thorough test ofthe packaged part is conducted before thefinished product is shipped.14Copyright 2012, Intel Corporation. All rights reserved.Intel, Intel logo and Intel Core are trademarks of Intel Corporation in the U.S. and other countries.