WIXLIB

STEPHEN J. FARIS192 Ruggles St.Westborough, MA 01581Home (508) 616 - 0385Cell (508) 335-4077sjfaris@aol.comSUMMARY Extensive experience in Microelectronics and Packaging for Systems on a Chip Technology(SoC)Experience with PC board electrical design issues.Worked extensively with Synopsys, Cadence and Mentor CAD tools.Verilog and VHDL coding experience.Experienced in DFT SCAN using Industry Tools like Mentor Fast Scan and DFTcompiler.Familiar with Signal Integrity at Board and Chip Level.Experienced with Synopsys Primetime.Experience with Cadence design tools such as Encounter, place and route tools like qplace and wroute,Signal Integity tools such as Celtic.Experienced with Synopsys Formality for Logical Equivalence Checking.Project management and applications engineering skillsExtensive work with Systems on a Chip and ASIC/FPGA ToolsFamiliar with Military Component Environmental and Electrical Test RequirementsFamiliar with Digital Communications Standards such as Ethernet/Sonet, PCI and PCI Express.Also other serial interfaces standards such as SATA, USB 2.0, and DIGRF.Extensive work on DFT/ATPG using Synopsys/Mentor ToolsCapable of leading design efforts, starting with a system level architecture, developing subsystemrequirements and leading a small development teamKnowledgeable of Linux/Unix/C and Windows application softwareExtensive experience with Perl and TCL scriptingVerification Experience using Modelsim , Verilog, and Systemverilog.Experienced with Register Management Software from Semifore Corp. This software describesthe logic structure of complex designs and writes out Verilog/VHDL Code, verification files,and documentation. EDUCATIONBSEE, University of Mass. DartmouthMSEE Program, Northeastern UniversityCourses in Microprocessors, C and C Industry Training Classes for various subjects.EXPERIENCEIntrinsix CorpOct 11 to presentWorked with CSR Compiler on a dozen complex IP devices to produce Verilog/VHDL code,simulation files anddocumentation. CSR Complier is Register Management Software from Semifore Corp. This software controls allassociated files used in SoC and ASIC design projects. Using this software, I worked on such complex devicesas Uarts, GPIO, Timers, Flash Controller, Ethernet and a USB otg device.1-4

Wizard Electronic Design ServicesJan 09 to Oct 11Started a company providing electronic design services to several small companies. For example, Iworked on testing of a Medical Infusion Pump and a Solar project for a start-up company. Also I madeproposals for new designs using embedded microprocessors such as TI’s MSP430.Availink Corp – Germantown, Md (Contract Assignment)Oct 08 to Jan. 09This work was a short term contract for Mentor Fastscan test vector development. The SoC will beused in set top boxes for a Chinese company. My work involved setting the required flow, resolvingcircuit problems and testing the scan vectors in NC Verilog. I resolved several major netlist issuespreventing production test vectors. I also contributed to the Test Specification Document. Also, Icontributed to the Primetime SI requirements document.Bitwave Semiconductor – Lowell, Ma (Contract Assignment)Staff Engineer/VerificationAug. 08 to Oct 08Responsible for the verification and simulation of an DIGRF ASIC design. This ASIC is a mixed Analogand Digital design using an 8051 and DSP Cores. The design incorporated all the DIGRF Standard3.09. The simulations used NC Verilog. The actual mixed signal ASIC was also verified using anAgilent Logic Analyzer, stimulus and analyzer probe specially designed for the DIGRF Standard. Majorfeatures of the standard were verified in NC Verilog and using the Agilent Equipment for DIGRF.Smartmodular Corp – Tewksbury, Ma (Contract Assignment)Staff Engineer/VerificationNov 07 to June 08Major responsibility was for a Xilinx FPGA Controller used for a High Performance Solid State DiskDrive. This work involved the RTL coding modification, Synthesis, Timing Analysis. This design wasover 2Million gates, with FIFOS and RAMS and 600 pins. Also, I setup a Modelsim Verification forRTL and gates with back annotation. I resolved some major timing problems and the design is now inproduction. This design had multi-million dollar potential for Smart.Safenet Corp – Danvers, Ma (Contract Assignment)Staff Engineer/Physical Design and VerificationJuly 06 to Sept 07My major responsibility is the synthesis and timing analysis of ARM based SoC’s used in securenetworking applications. Also, I was responsible for Logical Checking Software from Synopsys calledFormality. I used Formality to check RTL to gates and gates to gates for a 5 million gate SoC/ASIC.This involved writing TCL scripts for flow development. Then I debugged the logic differences in theRTL to gates or in the gates to gates logic from different netlists. For example, the netlist before testinsertion was checked against the netlist after test insertion to determine any significant logicaldifferences. I reported any discrepancies to the design team.2-4

Intel Corp –Hudson, Ma(Contract Assignment)June 05 to July 06SoC Staff EngineerPrimary responsibilty is the development of Primetime SI and CeltIC TCL scripting and flow development. Thiswork was in support of a large gate count Network Processor SoC Design. The design used 80nm CMOStechnology. I was responsible for generation of parasitics using Star-RCXT from Synopsys, and SRAM generationusing a custom flow. In addition, I used Synopsys Astro and Hercules to investigate layout issues. A large amountof TCL/Perl scripting was involved. Some Intel Standard Cell Library work was involved.Kawasaki Microelectronics America (Perm)Mar 04 to May 05SoC Staff EngineerLead support engineer for a 4Million Gate SoC design for an EPON(Ethernet Passive Optical Network)application. This was an SoC using the ARM922. My reponsibility included, synthesis, DFT, floorplanning andStatic Timing. This was the first SoC developed at the Kawasaki East Coast Facility. This design should result inmulti-dollar revenue stream for Kawasaki.Mitsubishi Electric (Renesas) (Perm)July 01 to Mar. 04ASIC/SoC Staff EngineerResponsible for ASIC physical design of SoCs and other ASICs using ARM Core CPU’s and internal Mitsubishi32 Bit Core Processors. Created single and multi-processor designs in high volume production using TSMC, andMitsubishi libraries and Fabs. Used Cadence and Synopsys(Avanti-Apollo) layout tools in timing driven mode.Developed timing sign off scripts using Primetime and Pearl, which provided system functional path and IOanalysis to meet PC board requirements. Provided full scan DFT using DFTCompiler/TetraMax and JTAGexpertise. This work lead to the first Mitsubishi Products for Fast Turn ASIC/SoC’s . Potential revenuegeneration is in the multi-million dollar range.3-4

IBM Corp.-Network Processor Division(Perm)June 00 to June 01Performed timing analysis of the Rainier Network Processor that had 10 million gate equivalents and used thePowerPC with 16 Packet Processors. Wrote complex TCL timing scripts and PERL scripts for EinsTimer(IBMinternal timing tool) to close timing on all internal paths. Defined the critical I/O timing parameters for thepublished Rainier Data Sheet Timing which was accomplished with EinsTimer, TCL scripts and a custom PERLscript. I/O timing was used by major accounts to design the PC board. The most critical timing was on the DoubleData Rate DRAM interface which involved extremely tight timing and careful analysis of the JEDEC DDRspecification. This work resulted in the first published timing information on this complex Network Processor.IBM planned to sell this product to many customers and expected revenue generation was in the muti-milliondollars range.3Com Corp-Switching Division(Contract/Perm)July 96 to June 00Performed ASIC Physical Design on many large ASICs for 3Coms Corebuilder product line including Synopsyssynthesis, timing analysis and floor planning. In conjunction with the ASIC chip development, wrote scripts inPERL, Unix and designed MAKE files. Experience with Avanti/Apollo, Synopsys-Design Compiler andPrimetime. Developed special PERL scripts to handle cell placement in order to meet tight timing paths bothwithin and outside the ASIC. This also required understanding timing analysis at the PC board level wheninterfacing with SRAM, specialized networking chips, and other ASICs. This work was 3Coms first attempt atfloorplanning of complex custom ASIC’s and as a result the Corebuilder product line shipped over 350 milliondollars using these ASICs.Quantum-Shrewsbury, Ma –Disk Drive(Contract)July 95 to June 96Performed design and support for a large ASIC using Viewlogic, Synopsys, and Viewsim. Responsibilitiesincluded script generation using Make and PEARL. This ASIC product was used a solid state disk drive thatshipped millions of units.Teradyne-Boston, Ma –IC Test Equipment (Contract)Oct. 94 to June 95Performed Verilog Coding and simulation using Cadence tools. Defined required specification of an ASIC usedin an advanced IC tester. The ASIC developed here was used in Teradyne’s Advanced Memory Testers. Thisgenerated millions of dollars of revenue.Chipcom-Southboro, Ma –Networking Equipment (Contract)July 94 to Oct. 94Performed Verification of Ethernet ASIC Design using Mentor Ample. Inserted full scan in an advanced ASICwith Mentor Fastscan and DFT Advisor.GTE-Needham, Ma –Telephone Equipment(Contract)Jan. 94 to June 94Setup test benches using VHDL for a large ASIC project. Set up DFT flows with Mentor and Synopsys tools foran ATM project. Included in this project was ASIC tools evaluation. This work resulted in the first ASICs for alarge GTE switch fabric.TEXAS INSTRUMENTS INC., Waltham, Ma(Perm)Feb. 87 to Dec. 93MEMBER TECHNICAL STAFFPerformed ASIC flow development using Mentor and Internal TI tools. Contributed to the development of ASICClients by providing expert advice and support. Responsible for technical support of TI's major ASIC customers.Included Field Application Engineering experience. Developed expertise in circuit simulation and design for testconcepts. Designed digital circuits for various customer applications using the TMS370. Trained on variousCAD tools such as Viewlogic, Mentor 8 and Ikos. This work resulted in development of Kodak and Xerox aslarge users of TI products and generated millions of dollars of revenue.4-4

SYNERTEK INC, Dover, Ma.(Perm)Oct. 78 to Dec. 87(Subsidiary of Honeywell)Field Application EngineerAs a Senior Field Application Engineer my duties included technical support of microprocessors, memory andstandard cell custom circuits. This required extensive knowledge of microprocessor development systems andassemble language programming. This expanded my knowledge of computer architecture, industrial applicationsand telecom. Provided support for the following microprocessors: NSC16000, 8085, 6500 and the Z8. This worklead to the generation of many new customers and millions of dollars in revenue.DIGITAL EQUIPMENT CORP., Marlboro, Ma.(Perm)Feb. 75 to Oct. 78Product Assurance EngineerAs product assurance engineer, I was responsible for the design assurance of the LSI-11/PDP-11 minicomputerand associated interface modules. I wrote product test plans and helped resolve design and application issueswith customers.5-4

Experienced with Synopsys Primetime. Experience with Cadence design tools such as Encounter, place and route tools like qplace and wroute, Signal Integity tools such as Celtic. Experienced with Synopsys Formality for Logical Equivalence Checking. Project management and applications engineering skills