WIXLIB

Modules listTable 3. SCM-i.MX 6SoloX modules listBlockBlock NameSubsystemBrief N2Flexible ControllerAreaNetworkConnectivityPeripheralsFuse BoxElectrical FuseArraySecurityGC400TGraphics EngineMultimediaPeripheralsGICGlobal InterruptControllerARM/ControlGISGeneral InterruptServicemoduleGeneral PurposeI/OModulesCamera, Display,&GraphicsSystem ControlPeripheralsprovides a full-duplex serial port for serialcommunication with a variety of serial devices,including industry-standard codecs, SPDIFtransceivers, and other processors. The ESAIconsists of independent transmitter andreceiver sections, each section with its ownclock generator. All serial transfers aresynchronized to a clock. Additionalsynchronization signals are used to delineatethe word frames. The normal mode of operationis used to transfer data at a periodic rate, oneword per period. The network mode is alsointended for periodic transfers; however, itsupports up to 32 words (time slots) per period.This mode can be used to build time divisionmultiplexed (TDM) networks. In contrast, theon-demand mode is intended for non-periodictransfers of data and to transfer data serially athigh speed when the data becomes available.The ESAI has 12 pins for data and clockingconnection to external devices.The CAN protocol was primarily, but not only,designed to be used as a vehicle serial databus, meeting the specific requirements of thisfield: real-time processing, reliable operation inthe Electromagnetic interference (EMI)environment of a vehicle, cost-effectivenessand required bandwidth. The FlexCAN moduleis a full implementation of the CAN protocolspecification, Version 2.0 B, which supportsboth standard and extended message frames.Electrical Fuse Array. Enables setup of bootmodes, security levels, security keys, and manyother system parameters. The fuses areaccessible through OCOTP CTRL interface.The GC400T is a graphics engine with separate2D and 3D pipelines to provide both 2D and 3Dacceleration. It supports DirectFB and GALAPIs. It supports OpenGL ES1.1/2.0 andOpenVG 1.1 APIs.The Global Interrupt Controller (GIC) collectsinterrupt requests from all i.MX 6SoloX sourcesand routes them to the ARM MPCore(s). Eachinterrupt can be configured as a normal or asecure interrupt. Software Force Registers andsoftware Priority Masking are also supported.This IP is part of the ARM Core complex.GIS can be used to automate the flow of datafrom the camera to the IO5GPIO6GPIO7Full FeatureFull FeatureFull FeatureFull FeatureFull FeatureUsed for general purpose input/output toexternal ICs. Each GPIO module supports 32bits of I/O.ReducedGPIO’s.SCM-i.MX 6SX Data Sheet for Industrial Products, Data Sheet: Technical Data, Rev. 0, 02/2017NXP SemiconductorsDownloaded from Arrow.com.7

Modules listTable 3. SCM-i.MX 6SoloX modules listBlockBlock NameSubsystemBrief DescriptionAvailabilityGPMIGeneral PurposeMemory InterfaceConnectivityPeripheralsFull FeatureGPTGeneral PurposeTimerTimer PeripheralsI2C-1I2C-2I2C-3I2C-4IOMUXCI2C InterfaceConnectivityPeripheralsThe GPMI module supports up to 8x NANDdevices and 60-bit ECC encryption/decryptionfor NAND Flash Controller (GPMI2). GPMIsupports separate DMA channels for eachNAND device.Each GPT is a 32-bit “free-running” or “set andforget” mode timer with programmableprescaler and compare and capture register. Atimer counter value can be captured using anexternal event and can be configured to triggera capture event on either the leading or trailingedges of an input pulse. When the timer isconfigured to operate in “set and forget” mode,it is capable of providing precise interrupts atregular intervals with minimal processorintervention. The counter has output comparelogic to provide the status and interrupt atcomparison. This timer can be configured to runeither with an external clock or an internalclock.I2C provide serial interface for external devices.Data rates of up to 400 kbps are supported.IOMUX ControlSystem ControlPeripheralsKPPKey Pad PortConnectivityPeripheralsLCDIFLCD InterfaceMultimediaPeripheralsLVDS (LDB)LVDS Multi-Mode nectivityPeripheralsMUMessaging UnitInterprocessorMnemonicThis module enables flexible IO multiplexing.Each IO pad has default and several alternatefunctions. The alternate functions are softwareconfigurable.KPP Supports 8x8 external key pad matrix.KPP features are: Open drain design Glitch suppression circuit design Multiple keys detection Standby key press detectionThe LCDIF provides display data for externalLCD panels from simple text-only displays toWVGA, 16/18/24 bpp color TFT panels. TheLCDIF supports all of these different interfacesby providing fully programmable functionalityand sharing register space, FIFOs, and ALUresources at the same time. The LCDIFsupports RGB (DOTCLK) modes as well assystem mode including both VSYNC andWSYNC modes.LVDS Display Bridge is used to connect anexternal LVDS display interface. LDB supportsthe following signals: One clock pair Four data pairsThe MLB interface module provides a link to aMOST data network, using the standardizedMediaLB protocol (MOST25, MOST 50).DDR Controller supports 32-bit LP-DDR2-800The MU module supports interprocessorNot available.Full FeatureFull FeatureReduced KPPpins.Full FeatureFull FeatureFull FeaturePoP memoryon FullFeatureFull FeatureSCM-i.MX 6SX Data Sheet for Industrial Products, Data Sheet: Technical Data, Rev. 0, 02/20178Downloaded from Arrow.com.NXP Semiconductors

Modules listTable 3. SCM-i.MX 6SoloX modules listBlockBlock NameSubsystemBrief DescriptionComm. & Synch.communication between the Cortex-A9 andCortex-M4 cores.The On-Chip OTP controller (OCOTP CTRL)provides an interface for reading, programming,and/or overriding identification and controlinformation stored in on-chip fuse elements.The module supports electrically-programmable(eFUSE) polyfuses. The OCOTP CTRL alsoprovides a set of volatile software-accessiblesignals that can be used for software control ofhardware elements, not requiring non-volatility.The OCOTP CTRL provides the primary uservisible mechanism for interfacing with on-chipfuse elements. Among the uses for the fusesare unique chip identifiers, mask revisionnumbers, cryptographic keys, JTAG securemode, boot characteristics, and various controlsignals, requiring permanent non-volatility.The On-Chip Memory controller (OCRAM)module is designed as an interface betweensystem’s AXI bus and internal (on-chip) SRAMmemory module.Internal RAM, which is accessed throughOCRAM memory controller.Secure/nonsecure internal RAM, interfacedthrough the CAAM. OCRAM S can be used bysoftware for state retention of the CPU andother hardware blocks.Generates 32.768 KHz clock from externalcrystal.The PCIe IP provides PCI Express Gen 2.0functionality.Integrated power management unit. Used toprovide power to various SoC domains.The pulse-width modulator (PWM) has a 16-bitcounter and is optimized to generate soundfrom stored sample audio images and it canalso generate tones. It uses 16-bit resolutionand a 4x16 data FIFO to generate sound.AvailabilityMnemonicOCOTP CTRLOTP ControllerSecurityOCRAMOn-Chip MemoryControllerData PathOCRAM 128KBOCRAM S16KBInternal RAMInternal MemorySecure/nonsecureRAMSecured InternalMemoryOSC32KHzOSC32KHzClockingPCIePCI Express 2.0PMUPower-Mgmt.ConnectivityPeripheralsData se WidthModulationQSPIQuad ot ROMResource DomainControllerSemaphoreInternal n/PiXel ProcessingPipelineROM alsA high-performance pixel processor capable of1 pixel/clock performance for combinedoperations, such as color-space conversion,alpha blending, gamma-mapping, and rotation.The PXP is enhanced with features specificallyfor gray scale applications.The Quad Serial Peripheral Interface(QuadSPI) block acts as an interface to one ortwo external serial flash devices, each with upto four bidirectional data lines.Supports secure and regular boot modesRDC module supports domain-based accesscontrol to shared resources.Supports hardware-enforced semaphores.Full FeatureFull FeatureFull FeatureFull FeatureFull FeatureNot availableFull FeatureFull FeatureFull FeatureFull FeatureFull FeatureFull FeatureFull FeatureSCM-i.MX 6SX Data Sheet for Industrial Products, Data Sheet: Technical Data, Rev. 0, 02/2017NXP SemiconductorsDownloaded from Arrow.com.9

Modules listTable 3. SCM-i.MX 6SoloX modules listBlockBlock NameSubsystemBrief DescriptionAvailabilitySEMA42 is similar to SEMA4 with the followingkey differences: SEMA42 increases the number of accessdomains from 2 to 15 SEMA42 does not have interrupt toindicate semaphore release RDC programming model supports theoption to require hardware semaphore forperipherals shared between domains.Signaling between the SEMA42 and RDCbinds peripherals to semaphore gateswithin SEMA42.The SAI module provides a synchronous audiointerface (SAI) that supports full duplex serialinterfaces with frame synchronization, such asI2S, AC97, TDM, and codec/DSP interfaces.The SDMA is multi-channel flexible DMAengine. It helps in maximizing systemperformance by off-loading the various cores indynamic data routing. It has the followingfeatures: Powered by a 16-bit Instruction-Set microRISC engine Multi-channel DMAsupporting up to 32 time-divisionmultiplexed DMA channels. 48 events with total flexibility to trigger anycombination of channels. Memory accesses including linear, FIFO,and 2D addressing. Shared peripherals between ARM andSDMA Very fast Context-Switching with 2level priority based preemptive multitasking. DMA units with auto-flush and prefetchcapability Flexible address managementfor DMA transfers (increment, decrement,and no address changes on source anddestination address). DMA ports can handle unit-directional andbi-directional flows (copy mode). Up to 8-word buffer for configurable bursttransfers for EMIv2.5. Support of byte-swapping and CRCcalculations. Library of Scripts and API is availableThe SJC provides JTAG interface, whichcomplies with JTAG TAP standards, to internallogic. The i.MX 6SoloX processors use JTAGport for production, testing, and systemdebugging. In addition, the SJC provides BSR(Boundary Scan Register) standard support,which complies with IEEE1149.1 andIEEE1149.6 standards. The JTAG port must beaccessible during platform initial laboratorybring-up, for manufacturing tests andFull lation/SharingSAI1SAI2SDMASmart DirectMemoryAccessSJCSystem JTAGControllerSystem ControlPeripheralsSystem ControlPeripheralsFull FeatureFull FeatureFull FeatureSCM-i.MX 6SX Data Sheet for Industrial Products, Data Sheet: Technical Data, Rev. 0, 02/201710Downloaded from Arrow.com.NXP Semiconductors

Modules listTable 3. SCM-i.MX 6SoloX modules listBlockBlock NameSubsystemBrief DescriptionAvailabilitytroubleshooting, as well as for softwaredebugging by authorized entities. The i.MX6SoloX SJC incorporates three security modesfor protecting against unauthorized accesses.Modes are selected through eFUSEconfiguration.Secure Non-Volatile Storage, including SecureReal Time Clock, Security State Machine,Master Key Control, andViolation/Tamper Detection and reporting.A standard audio file transfer format, developedjointly by the Sony and Phillips corporations.Has transmitter and receiver functionality.Full FeatureMnemonicSNVSSecure NonVolatileStorageSecuritySPDIFSony PMONTemperatureMonitorSystem ControlPeripheralsTVDECODETV Decoder ressSpace RT InterfaceConnectivityPeripheralsuSDHC1SD/MMC andConnectivitySSI1SSI2SSI3The SSI is a full-duplex synchronous interface,which is used on the AP to provide connectivitywith off-chip audio peripherals. The SSIsupports a wide variety of protocols (SSInormal, SSI network, I2S, and AC-97), bitdepths (up to 24 bits per word), and clock /frame sync options. The SSI has two pairs of8x24 FIFOs and hardware support for anexternal DMA controller in order to minimize itsimpact on system performance. The secondpair of FIFOs provides hardware interleaving ofa second audio stream that reduces CPUoverhead in use cases where two time slots arebeing used simultaneously.The Temperature sensor IP is used fordetecting die temperature. The temperatureread out does not reflect case or ambienttemperature. It reflects the temperature inproximity of the sensor location on the die.Temperature distribution may not be uniformlydistributed, therefore the read out value maynot be the reflection of the temperature value ofthe entire die.The TVDEC decodes NTSC/PAL input fromVADC analog front end and provides YUV888data CSI.The TZASC (TZC-380 by ARM) providessecurity address region control functionsrequired for intended application. It is used onthe path to the DRAM controller.Each of the UARTv2 modules support thefollowing serial data transmit/receive protocolsand configurations: 7- or 8-bit data words, 1 or 2 stop bits,programmable parity (even, odd or none) Programmable baud rates up to 5 Mbps.32-byte FIFO on Tx and 32 half-word FIFOon Rx supporting auto-baud Option to operate as 8-pins full UART,DCE, or DTE UART1/6 support 8-pin,UART2/3/4/5 support 4-pini.MX 6SoloX specific SoC characteristics: AllFull FeatureFull FeatureFull FeatureNot availableFull FeatureReducedfunctionalityfor UART1and UART2.uSDHC1 is notSCM-i.MX 6SX Data Sheet for Industrial Products, Data Sheet: Technical Data, Rev. 0, 02/2017NXP SemiconductorsDownloaded from Arrow.com.11

Modules listTable 3. SCM-i.MX 6SoloX modules listBlockBlock NameSubsystemBrief ced MultiMediaCard / SecureDigital HostControllerPeripheralsavailable.USBUniversal SerialBus 2.0ConnectivityPeripheralsVADCVideo ADCConnectivityPeripheralsfour MMC/SD/SDIO controller IPs are identicaland are based on the uSDHC IP. They are: Fully compliant with MMCcommand/response sets and PhysicalLayer as defined in the Multimedia CardSystem Specification,v4.5/4.2/4.3/4.4/4.41/ including highcapacity (size 2 GB) cards HC MMC. Fully compliant with SDcommand/response sets and PhysicalLayer as defined in the SD Memory CardSpecifications, v3.0 including high-capacitySDHC cards up to 32 GB. Fully compliant with SDIOcommand/response sets andinterrupt/read-wait mode as defined in theSDIO Card Specification, Part E1, v3.0 All four ports support: 1-bit or 4-bit transfermode specifications for SD and SDIOcards up to UHS-I SDR104 mode (104MB/s max) 1-bit, 4-bit, or 8-bit transfermode specifications for MMC cards up to52 MHz in both SDR and DDR modes (104MB/s max) However, the SoC level integration and I/Omuxing logic restrict the functionality to thefollowing: Instances #1 and #2 areprimarily intended to serve as interfaces toon-board peripherals. These ports areequipped with “Card detection” and “WriteProtection” pads and do not supporthardware reset. Instance #3 is intended toserve as the primary external card slot. Instance #4 is intended to be the primaryboot device via eMMC or SD, or to be asecondary external card slot. Instances #3and #4 do not have “Card detection” and“Write Protection” pads and do supporthardware reset. All ports can work with 1.8V and 3.3 V cards. There are twocompletely independent I/O powerdomains for Ports #1 and #2 in four bitconfiguration (SD interface). Port #3 isplaced in his own independent powerdomain and port #4 shares power domainwith some other interfaces.USB contains: Two high-speed OTG 2.0 modules withintegrated HS USB PHYs One high-speed Host module connected toHSIC USB portVideo ADC digitizes an analog video signal,such as one from an inexpensive analogcamera. The video signal can be selected fromone of four inputs, VIN0-VIN3, through registercontrol.MnemonicFull FeatureNot availableSCM-i.MX 6SX Data Sheet for Industrial Products, Data Sheet: Technical Data, Rev. 0, 02/201712Downloaded from Arrow.com.NXP Semiconductors

Modules listTable 3. SCM-i.MX 6SoloX modules listBlockBlock NameSubsystemBrief DescriptionAvailabilityWDOG1WDOG3Watch DogTimer PeripheralsReducedWDOG pins.WDOG2(TZ)Watch Dog(TrustZone)Timer PeripheralsXTALOSCCrystal OscillatorInterfaceClocks, Resets,and Power ControlThe Watch Dog Timer supports two comparisonpoints during each counting period. Each of thecomparison points is configurable to evoke aninterrupt to the ARM core, and a second pointevokes an external event on the WDOG line.The TrustZone Watchdog (TZ WDOG) timermodule protects against TrustZone starvationby providing a method of escaping normalmode and forcing a switch to the TZ mode. TZstarvation is a situation where the normal OSprevents switching to the TZ mode. Suchsituation is undesirable as it can compromisethe system’s security. Once the TZ WDOGmodule is activated, it must be serviced by TZsoftware on a periodic basis. If servicing doesnot take place, the timer times out. Upon atime-out, the TZ WDOG asserts a TZ mappedinterrupt that forces switching to the TZ mode. Ifit is still not served, the TZ WDOG asserts asecurity violation signal to the CSU. The TZWDOG module cannot be programmed ordeactivated by a normal mode software.The XTALOSC module connects to an externalcrystal to provide system clocks.MnemonicReducedWDOG2 pins.Full Feature3.1. Special signal considerationsThe figure below shows critical internal module connections.SCM-i.MX 6SX Data Sheet for Industrial Products, Data Sheet: Technical Data, Rev. 0, 02/2017NXP SemiconductorsDownloaded from Arrow.com.13

Electrical characteristicsFigure 3. SCM-i.MX6SX critical internal connections3.2. PMIC electrical deratingsThe MMPF0100 PMIC has been integrated into the

(CAVP) of National Institute of Standards and Technology (NIST) . Its DRBG validation number is 94 and its SHS validation number is 1455. CAAM also implements a Secure Memory mechanism. In i.MX 6SoloX processors, the security memory provided is 32 KB. Full Feature CCM GPC . SRC . Clock Control Module, General Power . Contro ller, Clocks, Resets,