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AS5247 Detailed DescriptionDetailed DescriptionThe AS5247 is a Hall-effect magnetic sensor using a CMOSlateral technology. The lateral Hall sensors convert themagnetic field component perpendicular to the surface of thechip into a voltage.The signals from the Hall sensors are amplified and filtered bythe analog front-end (AFE) before being converted by theanalog-to-digital converter (ADC). The output of the ADC isprocessed by the hardwired CORDIC (coordinate rotatingdigital computer) block to compute the angle and magnitudeof the magnetic vector. The intensity of the magnetic field(magnitude) is used by the automatic gain control (AGC) toadjust the amplification level for compensation of thetemperature and magnetic field variations.The internal 14-bit resolution is available by readout registervia the SPI interface. The resolution on the ABI output can beprogrammed for 10 or 11bits.The Dynamic Angle Error Compensation block corrects thecalculated angle regarding latency, by using a linear predictioncalculation algorithm. At constant rotation speed the latencytime is internally compensated by the AS5247, reducing thedynamic angle error at the SPI, ABI and UVW outputs. TheAS5247 allows selecting between a UVW / ABI output and aPWM-encoded interface on the W-pin or the I-pin.At higher speeds, the interpolator fills in missing ABI pulses andgenerates the UVW signals with no loss of resolution. Thenon-volatile settings in the AS5247 can be programmedthrough the SPI interface without any dedicated programmer.Power ManagementThe AS5247 can be either powered from a 5.0V supply using theon-chip low-dropout regulator or from a 3.3V voltage supply.The LDO regulator is not intended to power any other loads,and it needs a 1 μF capacitor to ground located close to the chipfor decoupling as shown in Figure 11.In 3.3V operation, VDD and VDD3V3 must be tied together. Inthis configuration, normal noise performance (ONL) is availableat reduced maximum temperature (125 C) by clearingNOISESET to 0 (default configuration). When NOISESET is set to1, the full temperature range is available with reduced noiseperformance (ONH).Figure 10:Temperature Range and Output Noise in 3.3V and 5.0V ModeVDD (V)NOISESETTemperature Range ( C)RMS Output Noise (degree)5.00-40 1500.0683.30-40 1250.0683.31-40 1500.082Page 10Document Feedbackams Datasheet[v1-10] 2016-Dec-05

AS5247 Detailed DescriptionFigure 11:5.0V and 3.3V Power Supply Options5.0V Operation4.5 - 5.5VVDDLDO100nF3.3V OperationVDD3V33.0 – 3.6V1µF100nFGNDVDDVDD3V3LDOGNDAS5247AS5247After applying power to the chip, the power-on time (tpon)must elapse before the AS5247 provides the first valid data.Dynamic Angle Error CompensationThe AS5247 uses 4 integrated Hall sensors on Bottom Die andTop Die, which produce a voltage proportional to theorthogonal component of the magnetic field to the die. Thesevoltage signals are amplified, filtered, and converted into thedigital domain to allow the CORDIC digital block to calculatethe angle of the magnetic vector. The propagation of thesesignals through the analog front-end and digital back-endgenerates a fixed delay between the time of measurement andthe availability of the measured angle at the outputs. Thislatency generates a dynamic angle error, represented by theproduct of the angular speed ω and the system propagationdelay (tdelay):(EQ1)DAE ω x tdelayThe dynamic angle compensation block calculates the currentmagnet rotation speed (ω) and multiplies it with the systempropagation delay (tdelay) to determine the correction angleto reduce this error. At constant speed, the residual systempropagation delay is tdelay DAEC.The angle represented on the PWM interface is notcompensated by the Dynamic Angle Error Compensationalgorithm. It is also possible to disable the Dynamic Angle ErrorCompensation with the DAECDIS setting. Disabling theDynamic Angle Error Compensation gives a noise benefit of0.016 degree rms. This setting can be advantageous for lowspeed ( under 100 RPM) respectively static positioningapplications.ams Datasheet[v1-10] 2016-Dec-05Page 11Document Feedback

AS5247 Detailed DescriptionSPI Interface (slave)The SPI interface is used by a host microcontroller (master) toread or write the volatile memory, as well as to program thenon-volatile OTP registers. The AS5247 SPI only supports slaveoperation mode. It communicates at clock rates up to 10 MHz.The AS5247 SPI uses mode 1 (CPOL 0, CPHA 1) to exchangedata. As shown in Figure 12, a data transfer starts with thefalling edge of CSn (CLK is low). The AS5247 samples MOSI dataon the falling edge of CLK. SPI commands are executed at theend of the frame (rising edge of CSn). The bit order is MSB first.Data is protected by parity.SPI TimingThe AS5247 SPI timing is shown in Figure 12.Figure 12:SPI Timing MOSI(Input)Page 12Document Feedbackdata[15]data[14]data[0]ams Datasheet[v1-10] 2016-Dec-05

AS5247 Detailed DescriptionFigure 13:SPI TimingParameterDescriptionMintLTime between CSn falling edge and CLK rising edge350nstclkSerial clock period100nstclkLLow period of serial clock50nstclkHHigh period of serial clock50nstclk/2nsTime between last falling edge of CLK and risingedge of CSntHMaxUnitstCSnHigh time of CSn between two transmissions350nstMOSIData input valid to falling clock edge20nstMISOCLK edge to data output valid51nsRelease bus time after CS rising edge.10nstOZSPI TransactionAn SPI transaction consists of a 16-bit command frame followedby a 16-bit data frame. Figure 14 shows the structure of thecommand frame.Figure 14:SPI Command FrameBitNameDescription15PARCParity bit (even) calculated on the lower 15 bits ofcommand frame14R/W0: Write1: Read13:0ADDRAddress to read or writeTo increase the reliability of communication over the SPI, aneven parity bit (PARC) must be generated and sent. A wrongsetting of the parity bit causes an parity bit error which is shownthe PARERR bit in the error flag register. The parity bit iscalculated from the lower 15 bits of the command frame. The16-bit command consists of a register address and read/writebit which indicates if the transaction is a read or write and theparity bit. Figure 15 shows the read data frame.ams Datasheet[v1-10] 2016-Dec-05Page 13Document Feedback

AS5247 Detailed DescriptionFigure 15:SPI Read Data FrameBitNameDescription15PARDParity bit (even) calculated on the lower 15 bits of the readdata frame14EF13:0DATA0: No command frame error command occurred1: Error occurredDataThe data is sent on the MISO pin. The parity bit PARD iscalculated by the AS5247 of the lower 15 bits of data frame. Ifan error is detected in the previous SPI command frame, the EFbit is set high. The SPI read is sampled on the rising edge of CSnand the data is transmitted on MISO with the next readcommand, as shown in Figure 16.Figure 16:SPI ReadCSnMOSIMISOPage 14Document FeedbackCommandCommandCommandCommandRead ADD[m]Read ADD[n]Read ADD[o]Read ADD[p]DataDataDataDATA (ADD[m])DATA (ADD[n])DATA (ADD[o])ams Datasheet[v1-10] 2016-Dec-05

AS5247 Detailed DescriptionFigure 17:SPI Write Data FrameBitName15PARC14013:0DATADescriptionParity bit (even)Always lowDataThe parity bit PARC is calculated from the lower 15 bits of dataframe.In a SPI write transaction, the write command frame is followedby a write data frame at MOSI. The write data frame consists ofthe new content of register which address is defined in thecommand frame.During the new content is transmitted on MOSI by the writedata frame, the old content is send on MISO. At the nextcommand on MOSI the actual content of the register istransmitted on MISO, as shown in Figure 18.Figure 18:SPI Write TransactionCSnCommandMOSIWrite ADD[n]Data to write into ADD[n]DATA (x)Data content ADD[n]MISOams Datasheet[v1-10] 2016-Dec-05DATA (ADD[n])CommandWrite ADD[m]New Data contentof ADD[n]DATA (x)Data to write into ADD[m]DATA (y)Data content ADD[m]DATA (ADD[m])CommandNextcommandNew Data contentof ADD[m]DATA (y)Page 15Document Feedback

AS5247 Detailed DescriptionVolatile RegistersThe volatile registers are shown in Figure 19. Each register hasa 14-bit address.Figure 19:Volatile Register o operation0x0001ERRFL0x0000Error register0x0003PROG0x0000Programming register0x3FFCDIAAGC0x0180Diagnostic and AGC0x3FFDMAG0x0000CORDIC magnitude0x3FFEANGLEUNC0x0000Measured angle without dynamic angleerror compensation0x3FFFANGLECOM0x0000Measured angle with dynamic angle errorcompensationReading the NOP register is equivalent to a nop (no operation)instruction for the AS5247.Figure 20:ERRFL (0x0001)NameRead/WriteBit PositionDescriptionPARERRR2Parity errorINVCOMMR1Invalid command error: set to 1 by reading orwriting an invalid register addressFRERRR0Framing error: is set to 1 when anon-compliant SPI frame is detectedReading the ERRFL register automatically clears its contents(ERRFL 0x0000).Page 16Document Feedbackams Datasheet[v1-10] 2016-Dec-05

AS5247 Detailed DescriptionFigure 21:PROG (0x0003)NameRead/WriteBit PositionDescriptionPROGVERR/W6Program verify: must be set to 1 forverifying the correctness of the OTPprogrammingPROGOTPR/W3Start OTP programming cycleOTPREFR/W2Refreshes the non-volatile memorycontent with the OTP programmed contentPROGENR/W0Program OTP enable: enablesprogramming the entire OTP memoryThe PROG register is used for programming the OTP memory.(See programming the zero position.)Figure 22:DIAAGC (0x3FFC)NameRead/WriteBit PositionDescriptionMAGLR11Diagnostic: Magnetic field strength too low;AGC 0xFFMAGHR10Diagnostic: Magnetic field strength toohigh; AGC 0x00COFR9Diagnostic: CORDIC overflowDiagnostics: Loops FinishedLF 0:internal offset loops not readyregulatedLF 1:internal offset loop finishedLFR8AGCR7:0N

1 CSn_T Digital Input SPI chip select (active low) 2 CLK_B Digital Input SPI Clock 3 CLK_T Digital Input SPI Clock 4 MISO_B Digital Output SPI master data input, slave output 5 MISO_T Digital Output SPI master data input, slave output 6 MOSI_B Digital Input SPI master data output, slave input 7 MOSI_T Digital Input SPI master data output, slave .