Rmg Wet Process Challenges And The Patterning Knobs Towards N5 And .

Transcription

RMG WET PROCESS CHALLENGES AND THE PATTERNING KNOBSTOWARDS N5 AND BEYOND LOGIC DEVICESYUSUKE ONIKI *, LARS-ÅKE RAGNARSSON, GUY VEREECKE, FARID SEBAAI, HAROLD DEKKERS,EUGENIO DENTONI LITTA, TOM SCHRAM, FRANK HOLSTEYNS, AND NAOTO HORIGUCHIimec, Kapeldreef 75, 3001 Leuven, Belgium, * Oniki.Yusuke@imec.beSPCC 2018, 10-11st Apr. 2018, Cambridge, MA, USPUBLIC

OUTLINE Introduction imec view of logic roadmap RMG scaling challenges RMG patterning development Tri-layer patterning scheme Digital wet etching of polycrystalline metal films RMG scaling and multi-Vt patterning knobs D&GR SiH4 soak “blocked” patterning Summary2

INTRODUCTION

IMEC VIEW OF LOGIC ROADMAPSTANDARD CELL & REPLACEMENT METAL GATE (RMG) SCALING“i”N: imec lSiSiSi/SiGeSi/SiGePP (poly pitch)56424236-42Track height7.5/6.57.5/6.55.5/4.54.X/3.XFP (fin pitch)32242116-21Lg (gate length)20161210-12MP (metal pitch)40322116-21iN10 FFiN5 FFiN5 FFiN5 GAAiN3 CFET PPFinGate Continuous std. cell scaling Device performance boostLgTrack heightiN7 FF Aggressive FP/Lg reduction neededGate contactRouting trackVdd/VssBuried Vdd/VssFP

TYPICAL RMG PATTERNING SCHEMEBARC PATTERNING (DRY) METAL REMOVAL (WET) Major challenges: Dummy poly removal Core/IO oxide patterning(IL formation) HK deposition (HfO2) HK cap dep (TiN) Si-cap anneal (SSA) Barrier dep (TaN) pWFM patterning nWFM patterning W CMP High aspect ratio BARC open etch (dry) WFM selective removal in limited spaces (wet)BARC/lithoBARC open5TiN removalBARC ash/clean

RMG PATTERNING CHALLENGESPATTERNING SPACE Limited spaces for filling and dry/wet etching, cleaning, rinsing and drying MG thickness reduction, eWF tuning knobs, novel patterning and optimized unit process neededSgSFF

RMG PATTERNING DEVELOPMENT

* T. Hopf (imec), SPIE 2017RMG TRI-LAYER PATTERNING Tri-layer e.g. PR/SOG/SOC* as the patterning mask Better gap-fill capability To minimize N/P boundary lateral etchN/P BOUNDARY LATERAL ETCHPRSOGSOGSOCSOC(TiN)NMOSTiNNMOSPMOSTri-layer approachTiNGH 150nm(TiN)SOG/SOC openGood gap-filling in the scaled Sg/SFFConventional PR/BARCSOCTiNPMOSNMOSPMOSNMOSTri-layer/litho (193i)2x FP Controlled N/P boundary BARCPMOSN/P boundary lateral etch

RMG TRI-LAYER PATTERNINGPOST SOC ASH CLEAN Need to optimize SOC ash/cleanw/ optimized o (193i)TiNNMOS(TiN)PMOSSOG/SOC openSOCTiNNMOS(TiN)PMOSSOG removal (HF)TaNorHfO2NMOSSOC(TiN)PMOSTiN removal (TBD)TaNorHfO2NMOSTiNPMOSSOC ash/clean

WFM WET SELECTIVE ETCHN/P BOUNDARY UNDERCUT Wet etch through the limited spaces (SFF/Sg) may need prolonged process Prolonged wet etch will induce N/P boundary undercut and damage HKMG material underneathMinimized overetch Prolonged etch Original N/P boundarySFFSgSOCTiNTaN or HfO2SOCSOCTiNTiNTaN or HfO2TaN or HfO2

DIGITAL WET ETCHING OF POLY CRYSTALLINE METAL FILMSCONCEPTRef. digital etch of semiconductors:III-V G. C. DeSalvo, JES 1996SiT. Hattori, JES 1998III-V J. Lin, IEEE EDL 2014III-V D. H. van Dorp, ECS JSSST 2015 Two-step self-limiting process 1. self-saturating metal oxide growth 2. highly selective oxide removalMetal OXincoming metal surfaceMetalOxidation time2. Highly selective oxide removalOxide/metal thicknessOxide/metal thickness1. Self-limiting oxide growthOXincoming metal surfaceMetalEtch time The ER determined by the formed OX thickness and etch cycle#

DIGITAL ETCHING OF TINFEASIBILITY dHPM (RT): self-limiting TiN etch ( self-limiting oxide growth) dHCl (HT): negligible TiN loss HPM-HCl cycle: digital etching of TiN demonstrated ( 0.66nm/cy)dHPM (RT)Hot HClHPM-HCl DE12

DIGITAL ETCHING OF TINTIN TRENCH STRUCTURE Digital etch (HPM-HCl) Conformal and uniform TiN etch demonstrated Less sensitive to the TiN grain boundaries Ref. one-step etch (APM) TiN surface roughening seenDigital etch (HPM-HCl cycle)One-step etch (APM)TiNG. Vereecke (imec), SPCC 2017

IMPACT ON ELECTRICAL PROPERTIES (MOSCAP)DIGITAL ETCH (HPM-HCL CYCLE) OF TIN ON HK AND TANTiN DE: 5cys HPM-HCl DE on HfO2Ref. STI patterning / channel dopingChemOX-IL (imec clean)ALD-HfO2 (1.5nm)ALD-TiN (2nm)TiN removal: 5cys HPM-HCl DEALD-TiN(1nm)/TiAl(3nm)/TiN(3nm)CVD-WGate etch TiN DE: 5cys HPM-HCl DE on TaN Ref. STI patterning / channel dopingChemOX-IL (imec clean)ALD-HfO2 (1.5nm)ALD-TaN (1nm)ALD-TiN (2nm)TiN removal: 5cys HPM-HCl DEALD-TiN(1nm)/TiAl(3nm)/TiN(3nm)CVD-WGate etchNo negative impact on electrical properties (CET, Vfb, Jg, .) observed

TIN DIGITAL ETCHINGCONFORMAL VS. PLUG ETCH Digital wet etching seems to be less sensitive to the grain boundaries and metal seam Open trench conformal etching Closed trench plug etching enables metal recess etchingDigital etch (HPM-HCl)One-step etch (APM)15

APPLICATIONSDIGITAL WET ETCHING METAL FILMSSelective metal removalReplacement metal gate (RMG)MG removal (TiN, TaN, TiAlC, .)Replacement metal contact (RMC) wrap-around silicide / dual silicideUnreacted metal removal (TiN/Ti, Ni, .)Controlled metal recessSelf-aligned gate contact (SAGC)SD contact recess (Co, Ru, .)Liner metal pull: Ti/TiNA. Steegen(imec) SEMICON West 2016Buried power rail (BPR)BPR metal recess (W, Ru, .)Liner metal pull: TiN, TaN, .Fully self-aligned via (FSAV)Mx metal recess (Cu, Co, Ru, .)Liner metal pull: TaN/Co, Ru, MnN.J. H. Franke (imec) SPIE 20173D NAND/SCMWL metal recess (W, Co, Ru, .)Liner metal recess:TiN, .WLS. M. Y. Sherazi (imec) ISPD 2016L.D. Piazza (imec) SEMICON Korea 2018

RMG SCALING & MULTI-VT PATTERNING KNOBS

RMG SCALING & MULTI-VT PATTERNING KNOBS D&GRDipole SiH4 soakO scavengingTiN patterningon HKnWFM blocked patterningFin CD trim inRMGHK 1st orHKMG 1stSkip TaN barrierCMP assisted RMGpatterningImprove electrostaticw/o Rext penaltyGo back to old tech.Allow merged nWFM 1nm SFF gainHKF: 3nm Sg gainHKMGF: no Sg limitProcess complexityI/O compatibilityNo Sg gainFEOL metal contamLow thermal budgetHKMG rem. bf. SDGAA incompatibilitySiH4KnobsProsVolumeless Vt tuningZero-thick Vt tuning 2nm SFF/Sg gainConsCorrosive materialsPatterning difficultyHM thickness scalingPost dry etch residueHM thickness scalingSC/LC loading?HK exposure/damageIL regrowthnWFM Al diffusion

D&GRDIFFUSION AND GATE REPLACEMENT (D&GR) FLOWVOLUME-LESS EWF TUNING D&GR* flow with n-type WF shifter e.g. MgO, LaO, .MaskMaskTiN-HMTiN-HMHfO2HfO2MgONMOS D&GR stack* R. Ritzenthaler (imec), IEDM 2014MgOMask patterningTiNMgOHfO2TiN/MgO removalTiNHfO:MgHfO2Drive-in annealHfO:MgHfO2TiN removal

D&GR RISK ASSESSMENT – 1/2CORROSION Corrosive and hygroscopic MgO, LaO Well optimized wet etching and rinsingsolutions aterLa-waterM. Pourbaix: “Atlas of Electrochemical Equilibria in Aqueous Solutions” (1974)Mg-water: pp. 141, La-water: pp. 193. D&GR

D&GRD&GR RISK ASSESSMENT – 2/2NON-SOLUBLE FLUORIDE RESIDUES Non-soluble fluoride residues tobe generated if HfO:Mg, Laexposed to fluorine containingchemistry (dry/wet)Gate 1st planar:Gate etch HK removal (HF/HCl) LaFx, MgFx difficult to remove Dry etch & post etch wet clean fluorine free chemistriespreferred Challenge/concern on PERR: MGEB, MGC, x-couple, gatecontact etches21Gate 1st FinFET:D&GR gate removal (HF APM)

SiH4 soakSIH4 SOAKZERO-THICKNESS EWF TUNING SiH4 soak: O scavenging from the TiN/HfO2 interface provides p-type Vt shift zero-thickness eWF tuning NP patterning done by a thin liner HM SiH4 soak e.g. SiH4 soak after SSA (sacrificial Si-cap anneal):L-Å Ragnarsson (imec), VLSI 2016SiH4SSASOC patterningSi-cap removalMask ash/clean22SiH4 soakSi-cap removal

BlockedpatterningNWFM BLOCKED PATTERNINGHT-SOC & CMP ASSISTED “BLOCKED” PATTERNINGClosedOpenLong ch. gap fillWLong channel(NMOS)Y. Kikuchi (imec), IEDM 2016 CMP assisted “blocked” patterning Enables closed gate patterning Need thermally stable mask e.g. HT-SOC No need for a wet metal etch!

ULTIMATE RMG SCALINGTOWARDS N5 AND BEYOND Ultimate RMG scaling and multi-Vt enabled bycombining several patterning knobs e.g. D&GR SiH4 soak blocked patterning Dummy poly removalCore/IO oxide patterningHK depositionD&GR HK cap depSSA/Masked SiH4 soak Barrier dep (can skip)nWFM blocked patterning W CMPN-LVT N-SVT N-HVT P-ch. 1.5nm24WTiNP-SVT2-2.5nm 1nm 4.5-6nm

SUMMARY

SUMMARYRMG WET PROCESS CHALLENGES AND THE PATTERNING KNOBS RMG challenge Not much space! RMG patterning development Implementing tri-layer patterning (PR/SOG/SOC) Digital wet etching of TiN successfully demonstrated RMG scaling & multi-Vt patterning knobs D&GR to enable zero-thickness eWF tuning SiH4 soak as volumeless eWF tuning Blocked patterning to pattern closed nWFMUltimate RMG scaling and multi-Vt patterning to be enabled by 26

PUBLIC

rmg wet process challenges and the patterning knobs towards n5 and beyond logic devices yusuke oniki *, lars-Åke ragnarsson, guy vereecke, farid sebaai, harold dekkers, eugenio dentoni litta, tom schram, frank holsteyns, and naoto horiguchi imec, kapeldreef 75, 3001 leuven, belgium, * oniki.yusuke@imec.be