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Digital MicroelectronicCircuits(361-1-3021 )Presented by: Dr. Alex FishLecture 5:Parasitic CapacitanceandDriving a LoadDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads1

Motivation Thus far, we have learned how to model our essentialbuilding block, the MOSFET transistor, and how to usethese building blocks to create the most popular logicfamily, Static CMOS.We analyzed the characteristics of a static CMOS inverter,including its Static and Dynamic Properties.We saw that both the delay and the power consumption ofa CMOS gate depend on the load capacitance of the gate.t pd 0.69ReqCLoadDigital Microelectronic Circuits2Pdynamic f C VDDThe VLSI Systems Center - BGULecture 5: Capacitances and Loads2

What will we learn today? Today, we will go back to our MOSFET transistor to try andunderstand what parasitic capacitances are inherent to itsstructure. Then, we will develop a model for equivalent capacitanceestimation for delay calculation of a CMOS inverter. Accordingly, we will examine the optimal sizing of a CMOSgate. And finally, we will develop a methodology for sizing achain of inverters to drive a large load.Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads3

What will we learn today?5.1 MOSFET Capacitance5.2 Inverter DelayCapacitance Model5.3 Driving a LoadDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads4

5.25.1 MOSFET Capacitance5.2 Inverter DelayCapacitance Model5.3 Driving a LoadSo back to our device, let’s see whatparasitic capacitances we have:MOSFETCAPACITANCEDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads5

MOSFET Capacitance One of the important parameters of a MOS Transistor is itscapacitance.The MOSFET has two major categories of capacitance:» Gate/Channel Capacitance – capacitance caused by the insulatingoxide layer under the gate.» Junction Capacitance – pn-Junction capacitance between thediffusions and the substrate.toxCGSn LCGCCSBCGDn CDBp-substrateDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads6

Gate Capacitance The Gate Capacitance includes:» Gate to Channel Capacitance, CGC:The main capacitance that isdependent on the region of operation. oxIn general:CGC WLtox CoxWL» Gate Overlap Capacitance, CGDO, CGSO:A constant (small) capacitance causedby gate overlap of the diffusions.CGSO CGDO WCOverlapDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads7

Gate Capacitance Looking at gate capacitance as a function of biasing showshow it changes.» In accumulation, the capacitance is across the oxide.» As VGS grows, the depletion layer decreases the capacitance(as if the dielectric gets longer)» Once the channel is formed, the capacitance jumps.» At pinch-off, the drain capacitance drops to zero.Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads8

Gate CapacitanceDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads9

Gate Capacitance To model this non-linear behavior, we will use thefollowing approximations:All capacitance istowards substrateCGB CoxWLCapacitancesymmetrically dividedbetween source and drainAll capacitance toSourceCoxWL 22CGCS CGCDCGCS CoxWL3Question: How do we relate to Velocity Saturation?Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads10

Junction (Diffusion) Capacitance The Junction Capacitance is the diffusion capacitance of theMOSFET.This is measured according to fabrication parametersCdiff Cbottom Cside walls C j Area C jsw Perimiter C j Ldiff W C jsw 2 Ldiff W Digital Microelectronic CircuitsDiffusion cap is non-linear andvoltage dependent.For simplicity, we will take it asconstant in this course.The VLSI Systems Center - BGULecture 5: Capacitances and Loads11

MOSFET Capacitance Summary Dependence of MOS capacitances on W and L:Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads12

MOSFET Capacitance SummaryGCGSCGS CGCS CGSOCGDDSCGD CGCD CGDOCGB CGCBCGBCSBCDBCSB CSdiffC DB C DdiffBDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads13

5.25.1 MOSFET Capacitance5.2 Inverter DelayCapacitance Model5.3 Driving a LoadOK, so we saw that the MOSFET has a bunch of non-linearparasitic capacitances, which makes them tough to use. Tosimplify life we’ll now develop an:INVERTER DELAY CAPACITANCE MODELDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads14

Capacitance Modeling As we saw, MOSFET capacitances are non-constant andnon-linear.Therefore, it is hard to solve a general equation for anarbitrary transition/operation.Instead, we will develop a simple model that willapproximate the capacitances during a specific transitionthat interests us.In this case, we are looking for the Load Capacitance touse when finding the gate delay.Therefore, we will apply a step function to the input of aninverter and approximate the capacitances according to theMOSFET parasitics we just learned.Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads15

Capacitance Modeling Let’s look at a CMOS inverter with allCits parasitic capacitances:GSPS» Considering the Gates of theGtransistors are the inputs to theBinverter, any capacitor touching theCGBPCGDPDgate should be consideredVinCGDNinput capacitance.D» Considering the Drains of thetransistors are connected to theCGBNGBinverter output, any capacitor touchingCGSNSthe Drains should be consideredoutput capacitance.Digital Microelectronic CircuitsThe VLSI Systems Center - BGUCSBPCDBPVoutCDBNLecture 5: Capacitances and LoadsCSBN16

Capacitance Modeling We have to differentiate between output (intrinsic)capacitances and load (extrinsic) capacitances.DriverLoadCwireCout,1Cin,2Cint CextOur total load capacitance is CLoad Cout ,1 Cwire Cin ,2Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads17

Intrinsic (Output) Capacitance We’ll now look at what makes up theintrinsic output capacitance of the driver.This is primarily made up of diffusioncapacitances:» Both drain-to-body capacitances have a terminalwith a constant voltage and the other connectedto the output.CDBPCDBP CDBN» For a simple computation, we will replace themwith an equivalent capacitance to ground.CDBN» These capacitances are very non-linear and wewill not go into their calculation in this course.Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads18

Intrinsic (Output) Capacitance How about feedthrough capacitance?CGSP CGBP» Taking the input step as ideal, the gate-to-sourceand gate-to-body capacitances don’t contribute tothe propagation delay.» The source-to-body capacitance is shorted tothe supply, so it doesn’t switch. CGDP CGDNWhat about the gate-to-drain capacitance?» While the gate voltage rises (Vin), the drain voltagedrops (Vout) and vice versa.» According to the Miller Effect, we can move thiscapacitance relative to ground, doubling its value.» This can be regarded as overlap capacitance, as CGSN CGBNfor the majority of the transition the devices are incutoff or saturation.Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads2(CGDP CGDN)19

The Miller Effect A capacitor experiencing identical, but oppositevoltage swings at both its terminals can bereplaced by a capacitor to ground, whose value istwice the original value.Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads20

Summary of Intrinsic Output CapDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads21

External Capacitance Now, to annotate the parasitics during switching, we willcascade another inverter after the first.We first add the Wire Capacitance.CGP2Then we add the gate capacitances ofthe second inverter.» These are approximately the oxidecapacitance times the area:P2P1CGN 2 CGP 2 COX WN 2 LN 2 WP 2 LP 2 N1» Again, we can just add the pMOS gatecapacitance to the general capacitance toground.Digital Microelectronic CircuitsThe VLSI Systems Center - BGUCWN2CGN2Lecture 5: Capacitances and Loads22

External Capacitance What happened to overlap capacitance and theMiller Effect on CGD2?» Remember that this is an approximate model, but » L Leff 2*Lov, so CG Cox*W*Ldrawn.» During the transient, for most of the time the load gate’stransistors are in cutoff or in linear.» Miller effect won’t appear, because the second gatewon’t switch until tpd1 is over. Therefore:» YES, CGD2 and CGS2 contribute to the load capacitance.» BUT, a good approximation is just CG2 COX*W*LDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads23

Summary of Next Stage Input CapDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads24

Parasitic Capacitances - Summary Altogether, as a very general approximation, we get:Cload 2(CGDP1 CGDN1 ) CDBP1 CDBN1 CGP 2 CGN 2 CWMiller DiffusionAn even more general approximationwith N fan-out gates gives us:Cload Cout Cwire N CinCGP2LoadP1 CDBP1P2CGDP1 CGDN1N1CDBN1 CWN2CGN2Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads25

Last Time CMOS Inverter Capacitance Model for tpd.Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads26

Last Time MOS Capacitance Model Cload Cout Cwire N Cin» Driver Cap (Cout or Cint): Diffusion Miller» Load Cap (Cin or Cg): Gate cap, no millerDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads27

5.35.1 MOSFET Capacitance5.2 Inverter DelayCapacitance Model5.3 Driving a LoadUp till now, we discussed device sizing with anoptimal fanout of 1. What happens if we want tocascade more gates to the output?DRIVING A LOADDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads28

External Capacitance Up till now, we assumed our inverter was only driving acopy of itself. This is known as intrinsic or unloaded delay.But we usually will have a larger fanout, and in somecases, we will need to drive large loads.Let’s remember how we defined our load capacitance:Cload Cdiff Coverlap C fanout Cwire DriverLoadCint CextCwire We can now write our delayequation according to thesecomponents.Cout,1Cin,2CintCextt pd 0.69ReqCload 0.69Req Cint Cext Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads29

Sizing Factor (S) t pd 0.69Req Cint Cext This means that if we add a largerload, our delay will increase. This is intuitive, as it meanswe have to supply more current from the same source.If we were to widen our transistors by a factor S, this woulddecrease our resistance and increase our intrinsic*capacitance.Cint S Cint Req* Req SDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads30

Sizing Factor (S)*Cint S Cint Req* Req St pd 0.69Req Cint Cext These two factors trade-off, which is why we get an optimalinverter size. * R *t pd ,unloaded 0.69Req* Cint 0.69 eq S Cint 0.69ReqCint S However, upsizing our gate doesn’t affect the externalcapacitance and therefore decreases the loaded delay.t*pd Cext Cext 0.69 SCint Cext 0.69ReqCint 1 t p 0 1 SSCSCint int ReqDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads31

Sizing Factor (S)C t p t p 0 1 ext SCint t p 0 0.69 ReqCintDigital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads32

Driving a Large Load So now we have a very large load to drive. We could just use a very large inverter.» But then someone would have to drive this largeinverter. So considering we start with a limited inputcapacitance, how should we best drive this load?Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads34

Inverter ChainInOutCL If CL is given:» How many stages are needed to minimize thedelay?» How to size the inverters? Anyone want to guess the solution?Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads35

Delay Optimization Problem #1 To solve an optimization problem, we need a set ofconstraints:» Load Capacitance.» Number of Inverters.» Size of input capacitance.Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads36

Delay Optimization Problem #1 To explore this problem, we must definea proportionality factor, γ. γ is a function of technology*, that describes therelationship between a gate’s input gate capacitance (Cg)and its intrinsic output capacitance (Cint):Cint Cg* γ is close to 1 for most submicron processes!Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads37

Delay Optimization Problem #1 CgNow, we will write the delay as a function of γ, and theeffective fanout, f:Cext Cext f t pd t p 0 1 t 1 C p 0 g CintfCgWe can see that the delay for a certain technology is only afunction of the effective fanout!Digital Microelectronic CircuitsThe VLSI Systems Center - BGULecture 5: Capacitances and Loads38

Inverter with Load So we see that the delayincreases with ratio of loadto inverter size: f t p t p 0 1 is the intrinsic delay of an unloaded inverter. γ is a technology dep

Digital Microelectronic Circuits The VLSI Systems Center - BGU Lecture 5: Capacitances and Loads External Capacitance Up till now, we assumed our inverter was only driving a copy of itself. This is known as intrinsic or unloaded delay. But we usually will have a larger fanout, and in some cases, we will need to drive large loads. Let’s remember how we defined our load capacitance: We can now .